The BQ76905 integrates Short Circuit in Discharge Protection (SCD) using a dedicated comparator that monitors the differential voltage across the SRN - SRP pins and triggers an SCD alert or fault when the voltage exceeds a programmable threshold VSCD. The VSCD threshold is programmable using the Protections:Current:Short Circuit in Discharge Protection Threshold configuration register, with available settings shown in Table 6-9. The SCD protection is enabled using the Settings:Protection:Enabled Protections A:[SCD] configuration bit.

The SCD circuitry triggers an alert signal when a short circuit event is first detected, then triggers a fault if it persists after a programmable detection delay, SCD_DLY, which is set by the Protections:Current:Short Circuit in Discharge Protection Delay configuration register. The fastest setting can result in detection of a short circuit with only comparator delay, which can be <1 μs depending on the overdrive of the threshold. The delay settings are shown in Table 6-10.

The SCD safety alert is not set in user readable registers until up to 50 μs after the event occurs, even though it was detected and the delay timer already started. When the SCD protection delay is set very short, such as the first three settings, the SCD safety status can actually trigger before the alert becomes visible in the Alarm Raw Status() or Safety Alert A() registers, and then the alert is cleared by the SCD safety status. When the SCD delay is set to a longer setting, the SCD safety alert is then generally visible.

When an SCD fault is triggered, the device turns off the DSG FET if configured for autonomous FET control in Settings:Protection:DSG FET Protections A[SCD]. The CHG FET can also be disabled autonomously based on setting in Settings:Protection:CHG FET Protections A[SCD]. The device recovers after a programmable delay given by Protections:Current:Recovery Time, which can be set from 1 second to 255 seconds in 1-second steps. A delay setting of 0 disables autonomous recovery based on time. Continual retrying of time-based recovery can be avoided by using the Current Protection Latch feature.

Depending on the system configuration, the user can utilize the CHG Detector signal to determine whether the load has been removed from the pack after the FETs have been disabled. For more details on this, see CHG Detector. In this case, if the load has been removed, then recovery can occur when the 0x009B PROT_RECOVERY() command is sent from the host with the [SCDREC] bit set.