SLUUCI8 November 2023 BQ76905
The BQ76905 device includes a 0x00 Control Status() command, which is primarily intended for legacy bqStudio auto-detection and is not recommended for customer usage. The 0x00 Control Status() command behaves similarly to 0x3E and 0x3F when written, accepting subcommand addresses. When this command is read back immediately after it has been written, it returns 0xFFA5 once.
The device also includes the 0x12 Battery Status() command, which reports various status information on the pack, as shown below.
Bit | Name | Description |
---|---|---|
15 | SLEEP | This flag asserts if the device is in SLEEP mode 0x0 = Device is not in SLEEP mode 0x1 = Device is in SLEEP mode |
14 | DEEPSLEEP | This flag asserts if the device is in DEEPSLEEP mode 0x0 = Device is not in DEEPSLEEP mode 0x1 = Device is in DEEPSLEEP mode |
13 | SA | This flag asserts if an enabled safety alert is
present. 0x0 = Indicates an enabled safety alert is not present 0x1 = Indicates an enabled safety alert is present |
12 | SS | This flag asserts if an enabled safety fault is present. 0x0 = Indicates an enabled safety fault is not present 0x1 = Indicates an enabled safety fault is present |
11-10 | SEC1:SEC0 | SEC1:0 indicate the present security state of the device. . When in SEALED mode, device configuration cannot be read or written and some commands are restricted. . When in FULLACCESS mode, unrestricted read and write access is allowed and all commands are accepted. 0x0 = 0: Device has not initialized yet. 0x1 = 1: Device is in FULLACCESS mode. 0x2 = 2: Unused. 0x3 = 3: Device is in SEALED mode. |
9 | RSVD0 | Reserved |
8 | FET_EN | This bit is set when the device is in autonomous FET
control mode. The default value of this bit is set by the
Settings:FET Options[FET_EN] bit in Data Memory upon exit of
CONFIG_UPDATE mode. Its value can be modified during operation using
the FET_ENABLE() subcommand. 0x0 = Device is not in autonomous FET control mode, FETs are only enabled through manual command. 0x1 = Device is in autonomous FET control mode, FETs can be enabled by the device if no conditions or commands prevent them being enabled. |
7 | POR | This bit is set when the device fully resets. It is
cleared upon exit of CONFIG_UPDATE mode. It can be used by the host
to determine if any register configuration changes were lost due to
a reset. 0x0 = Full reset has not occurred since last exit of CONFIG_UPDATE mode. 0x1 = Full reset has occurred since last exit of CONFIG_UPDATE and reconfiguration of any register settings is required. |
6 | SLEEP_EN | This bit indicates whether or not SLEEP mode is allowed based on configuration and commands. The [[Power Config[SLEEP_EN]]] bit sets the default state of this bit. The host can send commands to enable or
disable SLEEP mode based on system requirements. When this bit is set, the device can transition to SLEEP mode when other SLEEP criteria are met. 0x0 = SLEEP mode is disabled by the host. 0x1 = SLEEP mode is allowed when other SLEEP conditions are met. |
5 | CFGUPDATE | This bit indicates whether or not the device is in CONFIG_UPDATE mode. It is set after the SET_CFGUPDATE() subcommand is received and fully processed. Configuration settings can be changed only while this bit
is set. 0x0 = Device is not in CONFIG_UPDATE mode. 0x1 = Device is in CONFIG_UPDATE mode. |
4 | ALERTPIN | This bit indicates whether the ALERT pin is asserted (pulled low). 0x0 = ALERT pin is not asserted (stays in hi-Z mode). 0x1 = ALERT pin is asserted (pulled low). |
3 | CHG | This bit indicates whether the CHG driver is enabled. 0x0 = CHG driver is disabled. 0x1 = CHG driver is enabled. |
2 | DSG | This bit indicates whether the DSG driver is enabled. 0x0 = DSG driver is disabled. 0x1 = DSG driver is enabled. |
1 | CHGDETFLAG | This bit indicates the value of the debounced CHG Detector signal. 0x0 = CHG Detector debounced signal is low. 0x1 = CHG Detector debounced signal is high. |
0 | RSVD0 | Reserved |