SLUUCJ0 November 2023 BQ76907
Class | Subclass | Name | Type | Min | Max | Default | Unit |
---|---|---|---|---|---|---|---|
Settings | Protection | Both FET Protections B | H1 | 0x00 | 0xFF | 0x06 | Hex |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RSVD0_4 | RSVD0_3 | RSVD0_2 | RSVD0_1 | RSVD0_0 | VREF | VSS | REGOUT |
Description: This bit field configures which protections disable Both FETs.
Bit | Field | Default | Description |
---|---|---|---|
2 | VREF | 1 | VREF Measurement Check 0 = Both FETs are not disabled when protection is triggered. 1 = Both FETs are disabled when protection is triggered. |
1 | VSS | 1 | VSS Measurement Check 0 = Both FETs are not disabled when protection is triggered. 1 = Both FETs are disabled when protection is triggered. |
0 | REGOUT | 0 | REGOUT flag 0 = Both FETs are not disabled when protection is triggered. 1 = Both FETs are disabled when protection is triggered. |