SLUUCJ0 November 2023 BQ76907
The BQ76907 integrates low-side CHG and DSG FET drivers, which can directly drive low-side protection NFET transistors. The state of the drivers is reported by the 0x12 Battery Status()[CHG] and [DSG] bits. The device supports both series and parallel FET configurations, providing FET body diode protection when configured for a series FET configuration, if one FET driver is on, and the other FET driver is off. In this case, the DSG driver can be turned on to prevent FET damage if the battery pack is charging while the DSG FET is disabled. Similarly, the CHG driver can be turned on if the pack is discharging while the CHG FET is disabled. For more details, see Body Diode Protection.
The device can be configured for fully autonomous operation, in which case the device autonomously enables the protection FETs if no enabled protection status fault is present which has been configured to control the FETs, and no host command has been issued to force the FET off. Autonomous mode is enabled by setting the Settings:Configuration:FET Options[FET_EN] or sending the 0x0022 FET Enable() subcommand, which toggles the [FET_EN] bit. If [FET_EN] = 0, the FETs remain disabled until they are manually enabled by command.
Manual FET control is available using the 0x29 FET Control() command independent of the setting of [FET_EN]. The format of the 0x29 FET Control() command is shown below. The bits that force the FETs to be enabled are only available if the Settings:Configuration:FET Options[HOST_FETON_EN] is set, while the bits that force the FETs to be disabled are only available if the Settings:Configuration:FET Options[HOST_FETOFF_EN] is set.
Bit | Name | Description |
7-4 | RSVD | Reserved |
3 | CHG_OFF | CHG FET driver control. This bit only operates if the [HOST_FETOFF_EN] bit in data memory is set. 0x0 = CHG FET driver is allowed to turn on if other conditions are met. 0x1 = CHG FET driver is forced off. |
2 | DSG_OFF | DSG FET driver control. This bit only operates if the [HOST_FETOFF_EN] bit in data memory is set. 0x0 = DSG FET driver is allowed to turn on if other conditions are met. 0x1 = DSG FET driver is forced off. |
1 | CHG_ON | CHG FET driver control. This bit only operates if the [HOST_FETON_EN] bit in data memory is set. 0x0 = CHG FET driver is allowed to turn on if other conditions are met. 0x1 = CHG FET driver is forced on. |
0 | DSG_ON | DSG FET driver control. This bit only operates if the [HOST_FETON_EN] bit in data memory is set. 0x0 = DSG FET driver is allowed to turn on if other conditions are met. 0x1 = DSG FET driver is forced on. |
Note that body diode protection takes priority over the manual FET commands. If the user does not want body diode protection to take effect in this case, it can be disabled by clearing the Settings:Configuration:FET Options[SFET] data memory configuration bit.
The BQ76907 includes PWM drive capability on the CHG and DSG FET drivers, which allows them to limit the average current flowing in a charge or discharge mode. The DSG FET driver actively drives the DSG pin high or low, based on the driver control, so can implement relatively fast switching to turn on and off the DSG FET. If a charger is not attached, then the CHG driver can also implement relatively fast switching in PWM mode. If a charger is attached with voltage significantly above the pack voltage (which means the voltage on PACK- is below VSS), then the CHG FET gate voltage is generally driven to approximately VSS + 0.5 V quickly when first disabled, then settles to the lower PACK- voltage at a rate depending on the system capacitance. The drivers are not intended to both be used in PWM mode at the same time, it is recommended to only use one in PWM mode at a time. The 0x6A DSG FET Driver PWM Control() and 0x6C CHG FET Driver PWM Control() commands enable the drivers in PWM mode. These commands are only available if the Settings:Configuration:FET Options[PWM_EN] data memory configuration bit is set.
The BQ76907 provides an option for the device to autonomously disable the CHG FET when the device enters SLEEP mode. The device only enters SLEEP mode when pack current is below a programmable threshold. The DSG FET is generally enabled in this mode, but the CHG FET can be disabled to reduce the power flowing through the gate-source resistor around the CHG FET. When a significant charging or discharging current is detected, the device exits SLEEP mode, returning to NORMAL mode, and then re-enables the CHG FET unless other conditions prevent it. The state of the CHG FET in SLEEP mode is set by the Settings:Configuration:FET Options[SLEEPCHG] data memory configuration bit.