SLUUCO5A december 2022 – august 2023 BQ34Z100-R2
HDQ communication between a host device and target device uses a single-wire, open-drain interface. The communication protocol is asynchronous return-to-one referenced to VSS. A passive pullup resistance is required to pull the HDQ line to a high state when neither the host nor the target is pulling the line low during the two-way communication over the single-wire interface. The interface uses a command-based protocol where the host sends a command byte to the HDQ target device. The command directs the target either to store the next 8 bits of data received to a register specified by the command byte (write command), or to output the 8 bits of data from a register specified by the command byte (read command). Command and data bytes consist of a stream of bits that have a maximum transmission rate of 5 Kb/s. The least-significant bit of a command or data byte is transmitted first. The first 7 bits of the command word are the register address, and the last command bit transmitted is the read/write (R/W) bit. Figure 9-1 illustrates a typical HDQ read cycle.
The HDQ line may remain high for an indefinite period of time between each bit of address or between each bit of data on a write cycle. After the last bit of address is sent on a read cycle, the HDQ target starts outputting the data after the specified response time, t(RSPS). The response time is measured from the fall time of the command R/W bit to the fall time of the first data bit returned by the target and therefore includes the entire bit time for the R/W bit. (The response time is not the time after the last command bit before the first data bit of the response begins.) Because the minimum response time is equal to the minimum bit cycle time, this means that the first data bit may begin as soon as the command R/W bit time ends.
This communication protocol may be referred to as HDQ8 to distinguish it from the HDQ16 protocol used by some devices like the BQ2060 and BQ2063. The bit timing of HDQ16 is identical to that of HDQ8, except that 16 bits of data are written or read instead of 8 bits. The HDQ16 command word is still a 7-bit address plus a R/W bit.