If the host implements the HDQ communication using a discrete processor I/O port, the timing of the transmitted HDQ data and the sampling of the received HDQ data depends on the host processor timing of the transitions on the HDQ line. If the HDQ communication routine is interrupted during a communication, it may cause the transmitted times to stretch, and the received data may not be interpreted correctly.

One solution is to disable interrupts during HDQ communication critical times. When the host is sending the address or data, there is no restriction on the time between each bit, so host interrupts can be enabled during the high time between bits. Interrupts may need to be disabled during the low bit times to ensure that the bit low times meet the required HDQ timing constraints. After the last address bit (a R/W bit) is sent on a read, interrupts also must be disabled to ensure that the received data is sampled correctly. Interrupts must be disabled during the entire receipt of the 8 data bit times.

If disabling interrupts during HDQ communication critical times is not feasible, another approach is to leave interrupts enabled, but to have all enabled interrupts set a flag that can be read to determine whether an interrupt occurred during an HDQ communication. The strategy would be to stop the communication with a break and then retry the communication if an interrupt occurred during an HDQ communication. This method requires that there be a reasonable probability of completing an HDQ communication without an interrupt.