SLUUCO5A december 2022 – august 2023 BQ34Z100-R2
Bus cycles consumed by HDQ communication must not exceed the same budget as for I2C. HDQ uses all the same interrupts and process operations that I2C uses. The gauge firmware abstracts communication to be hardware-layer independent. However, it should be noted that each byte exchange for HDQ requires about 3.6 ms (address + data), so only about 280 transactions per second are possible. This communication rate would require ((140 + 100) µs × 280) equals 67 ms of CPU time per second. Most hosts only require reading 20 bytes in any one second. That data rate demands only around 5 ms of CPU time.