SLUUCP8 June 2024 BQ41Z50
Class | Subclass | Name | Type | Min | Max | Default | Unit |
---|---|---|---|---|---|---|---|
Settings | Fuse | Permanent Fail Fuse B | H1 | 0x00 | 0xFF | 0x00 | Hex |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RSVD | RSVD | RSVD | VIMA | VIMR | CD | IMP | CB |
Fuse blow action for PFStatus() bits: | ||
RSVD (Bits 7–5): Reserved. Do not use. | ||
VIMA (Bit 4): Voltage Imbalance Active | ||
1 = | Enabled | |
0 = | Disabled (default) | |
VIMR (Bit 3): Voltage Imbalance At Rest | ||
1 = | Enabled | |
0 = | Disabled (default) | |
CD (Bit 2): Capacity Degradation | ||
1 = | Enabled | |
0 = | Disabled (default) | |
IMP (Bit 1): Cell impedance | ||
1 = | Enabled | |
0 = | Disabled (default) | |
CB (Bit 0): Cell balancing | ||
1 = | Enabled | |
0 = | Disabled (default) |