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SLVA504A February 2012 – July 2021 DRV8243-Q1 , DRV8244-Q1 , DRV8245-Q1 , DRV8800 , DRV8801 , DRV8802 , DRV8803 , DRV8804 , DRV8805 , DRV8806 , DRV8811 , DRV8812 , DRV8813 , DRV8814 , DRV8818 , DRV8821 , DRV8823 , DRV8824 , DRV8825 , DRV8828 , DRV8829 , DRV8830 , DRV8832 , DRV8832-Q1 , DRV8833 , DRV8834 , DRV8835 , DRV8836 , DRV8837 , DRV8840 , DRV8841 , DRV8842 , DRV8843 , DRV8844 , DRV8870 , DRV8871 , DRV8872

1Sources of Power Dissipation in an Integrated Driver
1. 1.1 H-Bridge
  1. 1.1.1 H-Bridge Driver Using High-Side Recirculation
  2. 1.1.2 H-Bridge Driver Using Low-Side Recirculation
2. 1.2 Half Bridge
  1. 1.2.1 Half Bridge Driver Using High-Side Recirculation
  2. 1.2.2 Half Bridge Driver Using Low-Side Recirculation
2Example Calculation
1. 2.1 H-Bridge
  1. 2.1.1 High-Side Recirculation Example
  2. 2.1.2 Low-Side Recirculation Example
2. 2.2 Half Bridge
  1. 2.2.1 Half-Bridge High-Side Recirculation Example
  2. 2.2.2 Half-Bridge Low-Side Recirculation Example
3References
4Revision History

1.1.2 H-Bridge Driver Using Low-Side Recirculation

Figure 1-2 H-Bridge Using Low-Side Recirculation

Figure 1-2 shows the switching sequence of a full bridge in PWM regulation between HS1 - load - LS2 (region # 1) and LS1 - load - LS2 (region # 5) with other transitions (region # 2, 3, and 4 for rising edge and region # 6, 7, and 8 for falling edge). The power dissipation on each FET is as follows:

Table 1-2 Power Dissipation for H-Bridge with Low-Side Recirculation

Region	Time ratio within PWM cycle	LS2 [W]	LS1 [W]	HS1 [W]
1	D₁	R_ON × I_L²	0	R_ON × I_L²
2	V_M/SR_LSOFF x f_PWM	R_ON × I_L²	0	0.5 x V_M x I_L
3	t_{DEAD_LSOFF}x f_PWM	R_ON × I_L²	V_D x I_L	0
4	V_D/SR_HSON x f_PWM	R_ON × I_L²	0.5 x V_D x I_L	0
5	(1 - D)₁	R_ON × I_L²	R_ON × I_L²	0
6	V_D/SR_HSOFF x f_PWM	R_ON × I_L²	0.5 x V_D x I_L	0
7	t_{DEAD_LSON}x f_PWM	R_ON × I_L²	V_D x I_L	0
8	V_M/SR_LSON x f_PWM	R_ON × I_L²	0	0.5 x V_M x I_L

If the slew time is significant portion of the PWM period, we recommend to adjust the duty cycle number based on slew times for regions # 1 and 5.

In Table 1-2,

R_ON = FET on-resistance [ohm]
f_PWM = PWM switching frequency [Hz]
V_M = Supply voltage to the driver [V]
I_L = Load current [A]
D = PWM duty cycle between 0 and 1
SR_HSOFF = Output voltage slew rate during rise when HS1 is turned off [V/sec]
SR_HSON = Output voltage slew rate during fall when HS1 is turned on [V/sec]
V_D = FET body diode forward bias voltage [V]
t_{DEAD_HSOFF} = dead time after HS1 has been turned off [sec]
t_{DEAD_HSON} = dead time before HS1 is turned on [sec]
SR_LSON = Output voltage slew rate during rise when LS1 is turned on [V/sec]
SR_LSOFF = Output voltage slew rate during fall when LS1 is turned off [V/sec]

If we assume power dissipation in regions #4 and #6 are negligible, slews rate match for rising and falling edges, dead times are equal, then power dissipation for each FET can be approximated as follows:

P_LS2 = R_ON × I_L²
P_HS2 = 0
P_LS1 = [R_ON × I_L² x (1-D)] + [2 x V_D x I_L x t_DEADx f_PWM]
P_HS1 = [R_ON × I_L² x D] + [V_M x I_L x (V_M / SR) x f_PWM]

For estimating power dissipation for load current flow in the reverse direction, identical equations apply, with only swapping of HS1 with HS2 and LS1 with LS2.