4 Depth, Range, and LET_EFF Calculation

Figure 4-1 Generalized Cross-Section (Left) of the LBC7 Technology BEOL Stack on the TPS7H2201-SP. GUI of RADsim Application (Right)

The TPS7H2201-SP is fabricated in the TI Linear BiCMOS 7, 250 nm process with a back-end-of-line (BEOL) stack consisting of four levels of aluminum. The total stack height from the surface of the passivation to the silicon surface is 13.98 µm based on nominal layer thickness as shown in Figure 4-1. Accounting for energy loss through the 1 mil thick Aramica ( Kevlar®) beam port window, the 40-mm air gap, and the BEOL stack over the TPS7H2201-SP, the effective LET (LET_EFF) at the surface of the silicon substrate and the depth and ion range was determined with the custom RADsim-IONS application (developed at Texas Instruments and based on the latest SRIM2013 [9] models). Table 4-1 lists the results.