2 Single-Event Effects

The primary destructive single-event effect (DSEE) events of interest in the TPS7H2201-SP are single-event latch-up (SEL), single-event burn-out (SEB), and single-event gate rupture (SEGR). In mixed technologies such as the Linear BiCMOS 7 process used for the TPS7H2201-SP, the CMOS circuitry introduces a potential for SEL, SEB, and SEGR susceptibility.

SEL can occur if excess current injection caused by the passage of an energetic ion is high enough to trigger the formation of a parasitic cross-coupled PNP and NPN bipolar structure (formed between the p-sub and n-well and n+ and p+ contacts) [1, 2]. The parasitic bipolar structure initiated by a single-event creates a high-conductance path (inducing a steady-state current that is typically orders-of-magnitude higher than the normal operating current) between power and ground that persists (is latched) until power is removed or until the device is destroyed by the high-current state. For the design of the TPS7H2201-SP, SEL-susceptibility was reduced by maximizing anode-cathode spacing (tap spacing) while increasing the number of well and substrate ties in the CMOS portions of the layout to minimize well and substrate resistance effects. Additionally, junction isolation techniques were used with buried wells and guard ring structures isolating the CMOS p-wells and n-wells (3, 4). The design techniques applied for SEL-mitigation were sufficient as the TPS7H2201-SP exhibited absolutely no SEL with heavy-ions of up to LET_EFF = 75 MeV-cm² / mg at fluences in excess of 10⁷ ions / cm² and a die temperature of 125°C.

SEB is similar to the SEL and occurs when the parasitic BJT of the DMOSFET is turned on by the heavy-ion strike. DMOS are susceptible to SEB and SEGR while on the off state, however, for the sake of sanity, the device was also evaluated on all possible cases (enable and disable). When a heavy ion with sufficient energy hits the p body, it creates an excess charge inducing a voltage drop. This voltage drop forward biases the emitter-base junction of the parasitic NPN (formed by the N+ source, the P base region, and the N-drift region). If this happens when the DMOSFET is under a high drain bias, a secondary breakdown of the parasitic npn BJT can occur, creating permanent damage of the DMOS (6). When the heavy-ion hits the neck region of the DMOS (under the gate), it creates electron hole-pairs on the oxide and silicon. Drift separates the excess electrons and holes due to the positive bias field on the drain to source of the DMOS. Holes are driven upward to the dioxide while the electrons are transported toward the drain. The collected holes on the dioxide create an equal image of electrons on the opposite side of the gate dioxide. Since the charge injection and collection after an event is faster than the transport and recombination of the e-h pairs, a voltage transient can be developed across the gate oxide. If this build-up voltage is higher than the oxide breakdown, permanent damage can be induced on the oxide, creating a destructive gate rupture (7). The TPS7H2201-SP was tested for SEB and SEGR at LET_EFF = 75 MeV-cm² / mg, fluences of ≥ 10⁷ ions/cm², die temperature of 20–25°C, and V_IN = 7 V. No increment on the V_IN current was observed, also any functionality malfunction was observed, demonstrating that the TPS7H2201-SP is SEB and SEGR-free.