5 Depth, Range, and LET_EFF Calculation

Figure 5-1 Generalized Cross Section of the BiCMOS Technology BEOL Stack on the TPS7H4001-SP [Left] and GUI of RADsim Application Used to Determine Key Ion Parameters [Right]

The TPS7H4001A-SP is fabricated in the TI Linear BiCMOS 250-nm process with a back-end-of-line (BEOL) stack consisting of four levels of standard thickness aluminum metal on a 0.6-µm pitch and damascene copper (Cu). The total stack height from the surface of the passivation to the silicon surface is 13.5 µm based on nominal layer thickness as shown in Figure 5-1. No polyimide or other coating was present; the uppermost layer was the nitride passivation layer (PON). Accounting for energy loss through the 1-mil thick Aramica beam port window, the 40-mm (30-mm for ¹⁶⁵Ho) air gap, and the BEOL stack over the TPS7H4001-SP, the effective LET (LET_EFF) at the surface of the silicon substrate, the depth, and the ion range was determined with the custom RADsim - IONS application (developed at Texas Instruments and based on the latest SRIM-2013 [7] models). The results are shown in Table 5-1. The stack was modeled as a homogeneous layer of silicon dioxide (valid since SiO2 and aluminum density are similar).