SLVAEM2A January 2020 – March 2021 TPS3700-Q1

4 Pin Failure Mode Analysis (Pin FMA)

This section provides a Failure Mode Analysis (FMA) for the pins of the TPS3700-Q1 (DDC and DSE package). The failure modes covered in this document include the typical pin-by-pin failure scenarios:

Pin short-circuited to Ground (see Table 4-2 and Table 4-6.)
Pin open-circuited (seeTable 4-3 and Table 4-7)
Pin short-circuited to an adjacent pin (see Table 4-4 and Table 4-8)
Pin short-circuited to VDD (see Table 4-5 and Table 4-9)

Table 4-2 through Table 4-9 also indicate how these pin conditions can affect the device as per the failure effects classification in Table 4-1.

Table 4-1 TI Classification of Failure Effects

Class	Failure Effects
A	Potential device damage that affects functionality
B	No device damage, but loss of functionality
C	No device damage, but performance degradation
D	No device damage, no impact to functionality or performance

Following are the assumptions of use and the device configuration assumed for the pin FMA in this section:

Unless otherwise specified, it is assumed that the voltages applied to all the pins are within the Recommended Operating Range specified in the TPS3700-Q1 data sheet.
VDD = 5 V
OUTA and OUTB pulled-up to VDD unless stated otherwise.