1 Introduction

High speed RF transceiver’s integrated Phase-Locked Loop (PLL)/VCO and DAC supply rail are sensitive to power supply spurious and noise. Load transient ripple on the power supply directly impacts the data converter performance. One such real application example is Time Division Duplex (TDD) mode in which RX and TX channel toggle causes dynamic load transient thus resulting in supply ripple which couples into signal spectrum causing side band multiplicative spurious affecting Spurious Free Dynamic Range (SFDR) and Error Vector Magnitude (EVM).

The most common solution to minimize that ripple and noise is to use linear power supplies cascaded to the DC-DC output rail. LDO based solutions come at the disadvantage of impacting power efficiency losses which becomes more challenging to manage in systems having multiple AFEs.

An alternative approach which is discussed in this application note is powering noise and ripple sensitive rails directly from the DC-DC output by restricting supply ripple within allowed limits.

Compared to a linear supply, there are two big advantages of using a DC-DC converter alone: the reduction in power loss and the size of the power supply. To use a DC-DC converter alone requires careful consideration of the switching supply control topology, as well as the design and layout of the DC-DC converter.

This application note uses the AFE8092 as an example of a high-performance RF sampling transceiver where the 1.8-V and 1.2-V supplies have been changed from a DC-DC converter plus LDO approach to a DC-DC converter-only approach. This methodology can be used for many other noise sensitive applications as well. The TPS62913 low-ripple and low-noise buck converter used in this application note is specifically designed to help engineers design power supplies that meet the noise and ripple requirements for noise sensitive applications.