SLVAF52B July   2021  – November 2021 AFE8092 , TPS62913

 

  1.   Trademarks
  2. 1Introduction
  3. 2System Description
    1. 2.1 AFE80xx Noise and Ripple Requirements
    2. 2.2 AFE80xx Supply Settling and EVM for TDD Operations
    3. 2.3 Block Diagram
      1. 2.3.1 Proposed Power Architecture
      2. 2.3.2 Power Sequencing
    4. 2.4 Power Supply Design Consideration
  4. 3Tests and Results
    1. 3.1 Test Methodology
      1. 3.1.1 Phase Noise (Transmit) (dBc/Hz)
      2. 3.1.2 EVM for Frequency Division Multiplexing (FDD) Mode(%)
      3. 3.1.3 EVM for TDD Mode(%)
      4. 3.1.4 Receive (RX) Spectrum (Power Supply Spurious)
      5. 3.1.5 Power Efficiency
    2. 3.2 Test Conditions
    3. 3.3 Test Results
      1. 3.3.1 Phase Noise
      2. 3.3.2 EVM for FDD Mode
      3. 3.3.3 EVM for TDD Mode
      4. 3.3.4 RX Spectrum
      5. 3.3.5 Power Efficiency
  5. 4Conclusion
  6. 5References
  7. 6Revision History

3.3.5 Power Efficiency

To compare efficiency of proposed solution FDD and TDD 5G NR spectrum power consumption is observed using onboard INA226 monitoring bus voltage and group currents for 0.9-V, 1.2-V, 1.8-V and 3.3-V supply.

As shown in Table 3-1 in standby mode for 5-V Input supply the Power efficiency remains close to 92% while for FDD and TDD mode the total power efficiency is at 87.67% and 90%. For 12 V the standby, FDD and TDD modes the total power efficiency is at 85.2%, 87.3%, and 88.17%. With respect to traditional cascaded DC - DC plus LDO topology for all rails, the overall efficiency improvement observed is approximately 20%.

Table 3-1 Power Efficiency
Input voltage(V) Input current(A) Input power(W) Standby/FDD/TDD Volateg Label Output voltage(V) Output current(A) Output Power (W) (Voltage Group) Total Power(W) Proposed DC-DC Solution PoL Efficiency (%) Cascaded DC-DC + LDO (All Supply Rails) PoL Efficiency (%)
4.98 1.09 5.41 Standby vcc 0.9 0.91 0.66 0.61 5.02 92.77 74.76
vcc 3.3 3.29 0.47 1.55
vcc 1.2 1.19 0.70 0.83
vcc 1.8 1.79 1.06 1.91
pll 1.8 1.80 0.07 0.13
12.04 0.49 5.86 Standby vcc 0.9 0.91 0.66 0.60 5.01 85.42 71.15
vcc 3.3 3.29 0.47 1.55
vcc 1.2 1.19 0.69 0.82
vcc 1.8 1.79 1.06 1.91
pll 1.8 1.80 0.07 0.13
4.95 2.89 14.30 FDD vcc 0.9 0.96 3.82 3.67 12.78 89.38 73.66
vcc 3.3 3.29 0.47 1.55
vcc 1.2 1.14 3.75 4.28
vcc 1.8 1.78 1.76 3.14
pll 1.8 1.80 0.07 0.13
12.00 1.22 14.58 FDD vcc 0.9 0.97 3.83 3.69 12.81 87.85 65.42
vcc 3.3 3.29 0.47 1.55
vcc 1.2 1.14 3.75 4.29
vcc 1.8 1.78 1.77 3.14
pll 1.8 1.80 0.07 0.13
5.02 2.02 10.15 TDD vcc 0.9 0.94 2.49 2.35 9.25 91.13 68.11
vcc 3.3 3.29 0.47 1.55
vcc 1.2 1.16 2.39 2.79
vcc 1.8 1.79 1.36 2.43
pll 1.8 1.80 0.07 0.13
12.03 0.87 10.48 TDD vcc 0.9 0.94 2.49 2.35 9.27 88.43 67.33
vcc 3.3 3.29 0.47 1.56
vcc 1.2 1.16 2.41 2.80
vcc 1.8 1.79 1.36 2.43
pll 1.8 1.80 0.07 0.13
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