This section discusses how to narrow down in which area the problem might exist.

PoE start-up is tested first. This can have two oscilloscope shots to get everything needed. The waveforms needed are:

• VDD_RTN
• VSS_RTN *
• VC
• GATE (or Vds)
• Vout
• Iout (sometimes)

Figure 3-19 PoE Handshake

The waveforms in Figure 3-19 and Figure 3-20 show a successful PoE handshake (or not), and a successful DC/DC start-up. It is important to establish if the PD is negotiating power with a PSE. First, the waveforms confirm if detection is functioning as it should and that the PSE reads a proper detection. Next, the waveforms illustrate that VSS and RTN goes to 0 V, which means the internal pass MOSFET is working. This MOSFET can be damaged from ESD and surge events so it is important to confirm that the MOSFET is turning on after a detection and class signal.

Figure 3-20 PoE DC/DC Start-up

The VCC waveform confirms that the IC is receiving power. Remember that VCC is input power for the IC. If the VCC line is a triangle wave, then usually there is not enough effective capacitance on the VCC input. The next important piece of information to note is the GATE waveform. If VCC is above the threshold, but there is no switching, then the IC is broken internally. However, if there is switching, then it is confirmed that the IC is receiving power, that power is being internally regulated and is powering the gate to be switching. Thus far it is confirmed that the PD can successfully negotiate power, which means the PoE IC settings are probably correct. It is also confirmed that the IC is receiving power and the internal functions are being powered.

If the DC/DC converter is not starting up, then check the PoE settings, the DC/DC settings, the input bulk capacitor, the transformer, and the VC input.

The next thing to check is the switching components. First and foremost, check all MOSFETs in the system. Check the drain-to-ground and gate-to-ground of each MOSFET. Ensure they are all switching properly and the VDS and VGS is not exceeding the limits. Vary the input voltage and load to test the MOSFETs for maximum voltage and current. For example, do 57 Vin at no load and full load. Next, try 37 Vin at no load and full load.

Now, check the Vout signal. Vary the load of the system across the full range, and note any changes in the output behavior. The potential causes here can be an error in the feedback, too little output capacitance, or an error in the switching timing. Check for oscillations on the output as well.

After Vout, check the CS pin. This should be measured across the sense resistor – usually it is less than 1Ω, and placed directly next to the primary MOSFET. The waveform should look like a triangle wave. Ensure that the CS pin does not exceed the CS threshold before full load is applied to the output. Check the transformer primary inductance, the CS resistor size, and the primary FET. See Figure 3-21 for a reference of the CS waveform.

Figure 3-21 Current Sense Switching Waveform

Check the adapter input power (if applicable). Ensure that it properly powers the output and interacts with the PoE power as expected. Meaning, insure the adapter has the proper priority with PoE. For example, if the adapter is prioritized, then the PSE should remove power from the PD.

Finally, check the overall efficiency of the design. This is a good measure to tell the overall health of the design. If a component is too small, something is broken, something is too hot, something is too slow, and a number of other conditions can cause a drop in efficiency.