Figure 2-7 illustrates final flow of logic of the fault detection circuit.

Figure 2-7 Discrete Fault Detection Logic Flowchart

As Figure 2-7 shows, the comparator output (V_comp), is used to distinguish if a SG, OT or SB, OL has occurred. If a SB or OL has occurred, V_comp can be used to further distinguish between the two after PWM is pulled LOW. For SG, OT conditions, the fault pin is used along with the PWM pin to distinguish between a SG or OT fault.