6 Test Setup and Procedures

The device power (V)_IN was provided using the Agilent N6705C Power supply in a four-wire configuration. For the validation the device was tested using an "open-loop" configuration, under this configuration the V_SENSE and V_COMP voltages were forced externally using Channel 0 (CH 0) of two PXIe-4139 SMU (mounted on a PXI-1085 Chassis). For most of the testing, V_SENSE was set to 500 mV while V_COMP was set to 2 V. However, for F_SW = 1 MHz, V _COMPwas programmed to 1.7 V. For F_SW = 2 MHz, V_COMP was programmed to 1.4 V, PS = SP = LEB = 20 kΩ and R_SC = 15 kΩ. To minimize transient filtering on the OUTX and SRX signals, the only loading on the signals was due to the probes used to monitored these signals (approximately 11 pF). DCL pin was connected to GND through a 1-kΩ pull-down for all testing.

For SEL, SEB, and SEGR testing, the device was powered up to the maximum recommended operating voltage of 14 V. During the SEL testing the device was heated to 125°C by using a TDH35P10R0JE discrete power resistor soldered under the thermal vias on the bottom layer of the coupon card. Using a PXIe-4139 SMU, a current of 1.2 A was forced into the power resistor elevating the die temperature to 125°C. The temperature of the die was verified using thermal camera. During the SEL testing not a single current event was observed.

For the SEB/SEGR characterization, the device was tested under the Enabled and Disabled modes. For the SEB-OFF mode the device was disabled using the EN pin by forcing 100 mV (using CH 0 of a E36311A Keysight PS). When device was on, 5 V was forced to the EN pin. During the SEB and SEGR testing with the device in both the Enabled and Disabled mode, not a single OUTA (only trigger signal used) transient or input current event was observed.

For the SET characterization, the device was powered up to V_IN of 4, 12, and 14 V (TPS7H5002/3/4-SP were characterized at 12 V only). Internal and external clocks were used for the validation. For the external clock, a PXIe-5433 AWG was used to provide a 1-MHz pulse clock with 50% duty cycle and 0-V (low level) to 5-V (high level) logic levels into the SYNC pin of the TPS7H5001-SP. During the external clock testing, the RT pin was left floating. Internal switching frequency of 1 MHz was used for the data collection. To characterize the transient performance of the error amp, the SENSE and COMP pins of the device were tied together to operate the amplifier on unity gain. As with the DSEE in which the device can be permanently damaged, the complementary operation of OUTX to SRX is mandatory in synchronous rectifier applications. Cross conduction was tested to check if a transient in critical logic of the TPS7H5001-SP resulting in a momentary non-complementary operation of outputs can occur by using an AND gate tied to OUTA and SRA. Not a single cross conduction upset was recorded during this testing. In addition to the OUTX and SRX, the SS and the VLDO were also characterized for SET.

The SET events were monitored using two National Instruments™ scopes and setup as described in the following:

• PXIe-5110 used to trigger from SRA or SRB using a outside pulse-width trigger at ±30%.
• PXIe-5162 used to trigger from SS using a negative-edge trigger at 600 mV.

In addition an Tektronix™ DPO7104C was used to trigger from OUTA, COMP, or the AND gate used for cross-conduction. Only one signal at a time was used as the trigger. For OUTA, an outside pulse-width trigger at ±30% was used. For the COMP signal, a window trigger at ±10% from the nominal (0.6 V) was used. For the AND gate, a positive-edge trigger at 2.5 V was used (AND gate was powered up at 5 V). For details on SET testing, see Section 8.

All equipment other than the DPO7104C was controlled and monitored using a custom-developed LabVIEW™ program (PXI-RadTest) running on a HP-Z4™ desktop computer. The computer communicates with the PXI chassis through an MXI controller and NI PXIe-8381 remote control module. The DPO7104C manufacturer interface was used. The DPO was set to fast-frame for all SET data collection.

Table 6-1 shows the connections, limits, and compliance values used during the testing. Figure 6-1 shows a block diagram of the setup used for SEE testing of the TPS7H5001-SP.

All boards used for SEE testing were fully checked for functionality. Dry runs were also performed to make sure that the test system was stable under all bias and load conditions prior to being taken to the TAMU facility. During the heavy-ion testing, the LabVIEW control program powered up the TPS7H5001-SP device and set the external sourcing and monitoring functions of the external equipment. After functionality and stability was confirmed, the beam shutter was opened to expose the device to the heavy-ion beam. The shutter remained open until the target fluence was achieved (determined by external detectors and counters). During irradiation, the NI scope cards continuously monitored the signals. When the output pulse-width (OUTX and SRX) exceeded the pre-defined 30% pulse width trigger, a data capture was initiated. In addition to monitoring the time duration of the two scopes (OUTX and SRX), V_IN current and the 5-V signal from TAMU were monitored at all times. No sudden increases in current were observed (outside of normal fluctuations) on any of the test runs and indicated that no SEL or SEB/SEGR events occurred during any of the tests.

Figure 6-1 Block Diagram of the SEE Test Setup for the TPS7H5001-SP