10.1 Layout Guidelines

Layout is a critical part of good power-supply design. There are several signal paths that conduct fast-changing currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise or degrade the power-supply performance. To help eliminate these problems, the IN pin should be bypassed to ground with a low ESR ceramic bypass capacitor with an X5R or X7R dielectric.

Equivalent series inductance (ESL) and equivalent series resistance (ESR) must be minimized to maximize performance and ensure stability. Every capacitor (C_IN, C_OUT, C_NR/SS, C_FF) must be placed as close as possible to the device and on the same side of the PCB as the regulator itself.

Do not place any of the capacitors on the opposite side of the PCB from where the regulator is installed. The use of vias and long traces is strongly discouraged because these circuits may impact system performance negatively, and even cause instability.

10.2 Layout Example

Figure 29. Layout Example (DBV Package)

10.3 Power Dissipation

The ability to remove heat from the die is different for each package type, presenting different considerations in the printed circuit board (PCB) layout. The PCB area around the device that is free of other components moves the heat from the device to the ambient air. Performance data for JEDEC low- and high-K boards are given in Thermal Information. Using heavier copper increases the effectiveness in removing heat from the device. The addition of plated through-holes to heat-dissipating layers also improves the heatsink effectiveness.

Power dissipation depends on input voltage and load conditions. Power dissipation (P_D) can be approximated by the product of the output current times the voltage drop across the output pass element (V_IN to V_OUT), as shown in Equation 4.

Equation 4.

Power dissipation resulting from quiescent current is negligible. Excessive power dissipation triggers the thermal protection circuit.

Figure 30 shows the maximum ambient temperature versus the power dissipation of the TPS730. This figure assumes the device is soldered on a JEDEC standard, high-K layout with no airflow over the board. Actual board thermal impedances vary widely. If the application requires high power dissipation, having a thorough understanding of the board temperature and thermal impedances is helpful to ensure the TPS730 does not operate above a junction temperature of 125°C.

Figure 30. Maximum Ambient Temperature vs Power Dissipation

Estimating the junction temperature can be done by using the thermal metrics Ψ_JT and Ψ_JB, shown in Thermal Information. These metrics are a more accurate representation of the heat transfer characteristics of the die and the package than R_θJA. The junction temperature can be estimated with Equation 5.

Equation 5.

where

• P_D is the power dissipation shown by Equation 4.
• T_T is the temperature at the center-top of the IC package.
• T_B is the PCB temperature measured 1 mm away from the IC package on the PCB surface.

For more information about measuring T_T and T_B, see the application note Using New Thermal Metrics (SBVA025), available for download at www.ti.com.