12.1 Layout Guidelines

As for all switching power supplies, the layout is an important step in the design, especially at high peak currents and high switching frequencies. If the layout is not carefully done, the regulator could show stability problems as well as EMI problems. Therefore, use wide and short traces for the main current path and for the power ground tracks. The input capacitor, output capacitor, and the inductor should be placed as close as possible to the IC. Use a common ground node for power ground and a different one for control ground to minimize the effects of ground noise. Connect these ground nodes at any place close to one of the ground pins of the IC.

The feedback divider should be placed as close as possible to the control ground pin of the device. To lay out the control ground, using short traces is also recommended, separated from the power ground traces. This avoids ground shift problems, which can occur due to superimposition of power ground current and control ground current.

12.2 Layout Example

Figure 32. Layout Example

12.3 Thermal Considerations

Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires special attention to power dissipation. Many system-dependent issues such as thermal coupling, airflow, added heat sinks and convection surfaces, and the presence of other heat-generating components affect the power-dissipation limits of a given component.

Three basic approaches for enhancing thermal performance are listed below.

• Improving the power dissipation capability of the PCB design
• Improving the thermal coupling of the component to the PCB
• Introducing airflow in the system

The maximum junction temperature (T_J) of the TPS6112x devices is 150 °C. The thermal resistance of the 16-pin TSSOP package (PW) is R_ΘJA = 100.5°C/W. The 16-pin QFN (RSA) has a thermal resistance of R_ΘJA = 33.9°C/W, if the thermal pad is soldered and the board layout is optimized. Specified regulator operation is assured to a maximum ambient temperature T_A of 85°C. Therefore, the maximum power dissipation is about 647 mW for the TSSOP (PW) package and 1917 mW for the QFN (RSA) package; see Equation 10. More power can be dissipated if the maximum ambient temperature of the application is lower.

Equation 10.

If designing for a lower junction temperature of 125°C, which is recommended, maximum heat dissipation is lower. Using the above Equation 10 results in 1180 mW power dissipation for the RSA package and 400 mW for the PW package.