SLVS440C January   2003  – December 2014 TPS61045

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Dissipation Rating
    6. 6.6 Electrical Characteristics
    7. 6.7 Typical Characteristics
  7. 7  Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Peak Current Control
      2. 7.3.2 Softstart
      3. 7.3.3 Enable (CTRL Pin)
      4. 7.3.4 DAC Output (DO)
      5. 7.3.5 Digital Interface (CTRL)
      6. 7.3.6 UVLO
      7. 7.3.7 Thermal Shutdown
    4. 7.4 Device Functional Modes
  8. 8  Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Analog Adjusted Output Voltage
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Inductor Selection, Maximum Load Current
          2. 8.2.1.2.2 Setting the Output Voltage
          3. 8.2.1.2.3 Output Capacitor Selection
          4. 8.2.1.2.4 Input Capacitor Selection
          5. 8.2.1.2.5 Diode Selection
        3. 8.2.1.3 Application Curves
      2. 8.2.2 OLED Supply with Higher Output Current
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

5 Pin Configuration and Functions

DRB PACKAGE
(TOP VIEW)
PO_lvs440.gif
1. The exposed thermal pad is connected to PGND. Connect this pad directly with the GND pin.

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
CTRL 5 I Combined enable and digital output voltage programming pin. Pulling CTRL constantly high enables the device. When CTRL is pulled to GND, the device is disabled and the input is disconnected from the output by opening the integrated switch Q1. Pulsing CTRL low increases or decreases the output voltage. Refer to Application and Implementation for further information.
DO 3 O Internal DAC output. DO programs the output voltage through the CTRL pin. Refer to Application and Implementation for further information.
FB 4 I Feedback. FB must be connected to the output voltage-feedback divider.
GND 6 — Analog ground. GND must be directly connected to the PGND pin. Refer to Application and Implementation for further information.
L 1 O Drain of the internal input switch (Q1). Connect L to the inductor.
PGND 7 — Power ground
SW 8 I Drain of the integrated main switch Q2. SW is connected to the inductor and anode of the Schottky rectifier diode.
VIN 2 I Input supply pin
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