SLVS932F May   2009  – November 2014 TPS54325

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Simplified Schematic
  5. 5 Revision History
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 Handling Ratings
    3. 7.3 Thermal Information
    4. 7.4 Recommended Operating Conditions
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Soft Start and Pre-Biased Soft Start
      2. 8.3.2 Power Good
      3. 8.3.3 Output Discharge Control
      4. 8.3.4 Current Protection
      5. 8.3.5 Overvoltage and Undervoltage Protection
      6. 8.3.6 UVLO Protection
      7. 8.3.7 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 PWM Operation
      2. 8.4.2 PWM Frequency and Adaptive On-Time Control
      3. 8.4.3 Operation with VIN < 4.5 V
      4. 8.4.4 Operation With EN Control
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Output Voltage Resistors Selection
        2. 9.2.2.2 Output Filter Selection
        3. 9.2.2.3 Input Capacitor Selection
        4. 9.2.2.4 Bootstrap Capacitor Selection
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
      2. 12.1.2 Development Support
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

6 Pin Configuration and Functions

14-Pin
PWP PACKAGE
Top View
pinout_cropped_SLVS932.gif

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
VO 1 I Connect to output of converter. This terminal is used for On-Time Adjustment.
VFB 2 I Converter feedback input. Connect with feedback resistor divider.
VREG5 3 O 5.5 V power supply output. A capacitor (typical 1μF) should be connected to GND.
SS 4 I Soft-start control. A external capacitor should be connected to GND.
GND 5 –– Signal ground pin
PG 6 O Open drain power good output
EN 7 I Enable control input
PGND1, PGND2 8, 9 –– Ground returns for low-side MOSFET. Also serve as inputs of current comparators. Connect PGND and GND strongly together near the IC.
SW1, SW2 10, 11 O Switch node connection between high-side NFET and low-side NFET. Also serve as inputs to current comparators.
VBST 12 O Supply input for high-side NFET gate driver (boost terminal). Connect capacitor from this pin to respective SW1, SW2 terminals. An internal PN diode is connected between VREG5 to VBST pin.
VIN 13 I Power input and connected to high side NFET drain
VCC 14 I Supply input for 5 V internal linear regulator for the control circuitry
PowerPAD™ –– –– Thermal pad of the package. Must be soldered to achieve appropriate dissipation. Should be connected to PGND.
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