Table 3. Design Parameters

Table 4. Application Example – Component Proposals

8.2.2.1 BuckA Component Selection

8.2.2.1.1 Minimum ON Time, t_{ON min}

Equation 5.

This is higher than the minimum on-time specified (100 ns typical). Hence, the minimum duty cycle is achievable at this frequency.

8.2.2.1.2 Current-Sense Resistor R_SENSE

Based on the typical characteristics for V_SENSE limit with V_IN versus duty cycle, the sense limit is approximately 65 mV (at V_IN = 12 V and duty cycle of 5 V / 12 V = 0.416). Allowing for tolerances and ripple currents, choose V_SENSE with a maximum of 50 mV.

Equation 6.

Select 15 mΩ.

8.2.2.2 Inductor Selection L

As explained in the description of the buck controllers, for optimal slope compensation and loop response, the inductor should be chosen such that:

Equation 7.

K_FLR = Coil selection constant = 200

Choose a standard value of 8.2 µH. For the buck converter, the inductor saturation currents and core should be chosen to sustain the maximum currents.

8.2.2.3 Inductor Ripple Current I_RIPPLE

At nominal input voltage of 12 V, this inductor value causes a ripple current of 30% of I_{O max} ≈ 1 A.

Equation 8.

where

• V_IN = Input voltage
• V_OUT = Output voltage
• f_SW = Switching frequency
• L = Inductor

8.2.2.4 Output Capacitor C_OUTA

Select an output capacitance C_OUTA of 100 µF with low ESR in the range of 10 mΩ. This gives ∆V_O(Ripple) ≈ 15 mV and ∆V drop of ≈ 180 mV during a load step, which does not trigger the power-good comparator and is within the required limits.

Equation 9.

Equation 10.

Equation 11.

8.2.2.5 Bandwidth of Buck Converter f_C

Use the following guidelines to set frequency poles, zeroes and crossover values for a tradeoff between stability and transient response.

• Crossover frequency f_C between f_SW / 6 and f_SW / 10. Assume f_C = 50 kHz.
• Select the zero f_z ≈ f_C / 10.
• Make the second pole f_P2 ≈ f_SW / 2.

8.2.2.6 Selection of Components for Type II Compensation

Figure 15. Buck Compensation Components

Equation 12.

Use the standard value of R3 = 24 kΩ,

Where V_OUT = 5 V, C_OUTx = 100 µF, Gm_BUCK = 1 mS, V_REF = 0.8 V

K_CFB = 0.125 / R_SENSE = 8.33 S (0.125 is an internal constant)

Equation 13.

Use the standard value of 1.5 nF.

Equation 14.

The resulting bandwidth of buck converter, f_C:

Equation 15.

This is close to the target bandwidth of 50 kHz.

The resulting zero frequency f_Z1:

Equation 16.

This is close to the f_C / 10 guideline of 5 kHz.

The second pole frequency f_P2:

Equation 17.

This is close to the f_SW / 2 guideline of 200 kHz. Hence, the design satisfies all requirements for a good loop.

8.2.2.7 Resistor Divider Selection for Setting V_OUTA Voltage

Equation 18.

Choose the divider current through R1 and R2 to be 50 µA. Then

Equation 19.

and

Equation 20.

Therefore, R2 = 16 kΩ and R1 = 84 kΩ.

8.2.2.8 BuckB Component Selection

Using the same method as for V_BuckA produces the following parameters and components.

Equation 21.

This is higher than the minimum duty cycle specified (100 ns typical).

Equation 22.

∆I_ripple current ≈ 0.4 A (approximately 20% of I_{OUT max})

Select an output capacitance C_O of 100 µF with low ESR in the range of 10 mΩ. Assume f_C = 50 kHz.

Equation 23.

Equation 24.

Equation 25.

Equation 26.

Use the standard value of R3 = 30 kΩ.

Equation 27.

Equation 28.

Equation 29.

This is close to the target bandwidth of 50 kHz.

The resulting zero frequency f_Z1:

Equation 30.

This is close to the f_C guideline of 5 kHz.

The second pole frequency f_P2:

Equation 31.

This is close to the f_SW / 2 guideline of 200 kHz.

Hence, the design satisfies all requirements for a good loop.

8.2.2.9 Resistor Divider Selection for Setting V_OUT Voltage

Equation 32.

Choose the divider current through R1 and R2 to be 50 µA. Then

Equation 33.

and

Equation 34.

Therefore, R2 = 16 kΩ and R1 = 50 kΩ.

8.2.2.10 BUCKx High-Side and Low-Side N-Channel MOSFETs

An internal supply, which is 5.8 V typical under normal operating conditions, provides the gate-drive supply for these MOSFETs. The output is a totem pole allowing full voltage drive of V_REG to the gate with peak output current of 1.5 A. The reference for the high-side MOSFET is a floating node at the phase terminal (PHx), and the reference for the low-side MOSFET is the power-ground (PGx) terminal. For a particular application, select these MOSFETs with consideration for the following parameters: r_DS(on), gate charge Qg, drain-to-source breakdown voltage BVDSS, maximum dc current IDC(max), and thermal resistance for the package.

The times t_r and t_f denote the rising and falling times of the switching node and have a relationship to the gate-driver strength of the TPS43350x-Q1 and gate Miller capacitance of the MOSFET. The first term denotes the conduction losses, which are minimal when the on-resistance of the MOSFET is low. The second term denotes the transition losses, which arise due to the full application of the input voltage across the drain-source of the MOSFET as it turns on or off. They are lower at low currents and when the switching time is low.

Equation 35.

Equation 36.

In addition, during dead time t_d when both the MOSFETs are off, the body diode of the low-side MOSFET conducts, increasing the losses. The second term in the foregoing equation denotes this. Using external Schottky diodes in parallel to the low-side MOSFETs of the buck converters helps to reduce this loss.