SLVSAR7E June 2011 – October 2016
PRODUCTION DATA.
- 1 Features
- 2 Applications
- 3 Description
- 4 Revision History
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1
Buck Controllers: Normal Mode PWM Operation
- 7.3.1.1 Frequency Selection and External Synchronization
- 7.3.1.2 Enable Inputs
- 7.3.1.3 Feedback Inputs
- 7.3.1.4 Soft-Start Inputs
- 7.3.1.5 Current-Mode Operation
- 7.3.1.6 Current Sensing and Current Limit With Foldback
- 7.3.1.7 Slope Compensation
- 7.3.1.8 Power-Good Outputs and Filter Delays
- 7.3.1.9 Light-Load PFM Mode
- 7.3.2 Frequency-Hopping Spread Spectrum (TPS43351-Q1 Only)
- 7.3.3 Gate-Driver Supply (VREG, EXTSUP)
- 7.3.4 External P-Channel Drive (GC2) and Reverse-Battery Protection
- 7.3.5 Undervoltage Lockout and Overvoltage Protection
- 7.3.6 Thermal Protection
- 7.3.1
Buck Controllers: Normal Mode PWM Operation
- 7.4 Device Functional Modes
-
8 Application and Implementation
- 8.1 Application Information
- 8.2
Typical Application
- 8.2.1 Design Requirements
- 8.2.2
Detailed Design Procedure
- 8.2.2.1 BuckA Component Selection
- 8.2.2.2 Inductor Selection L
- 8.2.2.3 Inductor Ripple Current IRIPPLE
- 8.2.2.4 Output Capacitor COUTA
- 8.2.2.5 Bandwidth of Buck Converter fC
- 8.2.2.6 Selection of Components for Type II Compensation
- 8.2.2.7 Resistor Divider Selection for Setting VOUTA Voltage
- 8.2.2.8 BuckB Component Selection
- 8.2.2.9 Resistor Divider Selection for Setting VOUT Voltage
- 8.2.2.10 BUCKx High-Side and Low-Side N-Channel MOSFETs
- 8.2.3 Application Curves
- 9 Power Supply Recommendations
- 10Layout
- 11Device and Documentation Support
- 12Mechanical, Packaging, and Orderable Information
10 Layout
10.1 Layout Guidelines
This section lists the grounding and PCB circuit layout considerations.
10.1.1 Buck Converter
- Connect the drain of SWAH and SWBH MOSFETs together with the positive terminal of the input capacitor CIN. The trace length between these terminals should be short.
- Connect a local decoupling capacitor between the drain of SWxH and source of SWxL.
- The Kelvin-current sensing for the shunt resistor should have traces with minimum spacing, routed in parallel with each other. Place any filtering capacitors for noise near the IC pins.
- The resistor divider for sensing output voltage connects between the positive terminal of the respective output capacitor and COUTA or COUTB and the IC signal ground. Do not locate these components and their traces near any switching nodes or high-current traces.
10.1.2 Other Considerations
- Short PGNDx and AGND to the thermal pad. Use a star ground configuration if there is no ground plane present in the system. Use tie-ins for the EXTSUP capacitor, compensation-network ground, and voltage-sense feedback-ground networks to this star ground.
- Connect a compensation network between the compensation pins and IC signal ground. Connect the oscillator resistor (frequency setting) between the RT pin and IC signal ground. Do not locate these sensitive circuits near the dv/dt nodes; these include the gate-drive outputs and phase pins.
- Reduce the surface area of the high-current-carrying loops to a minimum by ensuring optimal component placement. Ensure the bypass capacitors are located as close as possible to their respective power and ground pins.
10.2 Layout Example
Figure 19. TPS4335x-Q1 Layout Example