11.1 Layout Guideline

• It is recommended to place the input capacitor as close as possible to the IC pins PVIN and PGND.
• The VOS connection is noise sensitive and needs to be routed as short and directly to the output pin of the inductor.
• The exposed thermal pad of the package, analog ground (pin 6) and power ground (pin 14, 15) should have a single joint connection at the exposed thermal pad of the package. This minimizes switch node jitter.
• The charge pump capacitor connected to CP and CN should be placed close to the IC to minimize coupling of switching waveforms into other traces and circuits.
• Refer to Figure 29 and the evaluation module User Guide (SLVU670) for an example of component placement, routing and thermal design.

11.2 Layout Example

Figure 29. TPS6209x Layout