SLVSAW2C March   2012  – October 2016

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Enable and Disable (EN)
      2. 8.3.2  Softstart (SS) and Hiccup Current Limit During Startup
      3. 8.3.3  Voltage Tracking (SS)
      4. 8.3.4  Short Circuit Protection (Hiccup-Mode)
      5. 8.3.5  Output Discharge Function
      6. 8.3.6  Power Good Output (PG)
      7. 8.3.7  Frequency Set Pin (FREQ)
      8. 8.3.8  Undervoltage Lockout (UVLO)
      9. 8.3.9  Thermal Shutdown
      10. 8.3.10 Charge Pump (CP, CN)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Pulse Width Modulation Operation
      2. 8.4.2 Power Save Mode Operation
      3. 8.4.3 Low Dropout Operation (100% Duty Cycle)
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Inductor Selection
        2. 9.2.2.2 Input and Output Capacitor Selection
        3. 9.2.2.3 Setting the Output Voltage
        4. 9.2.2.4 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guideline
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Related Links
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

6 Pin Configuration and Functions

RGT Package
16-Pin QFN
Top View
TPS62090 TPS62091 TPS62092 TPS62093 po_lvsaw2.gif

NOTE:

*The exposed thermal pad is connected to AGND.

Pin Functions

PIN I/O DESCRIPTION
NO. NAME
1, 2 SW I/O Switch pin of the power stage.
3 FREQ I This pin selects the switching frequency of the device. FREQ = Low sets the typical switching frequency to 2.8 MHz. FREQ = High sets the typical switching frequency to 1.4 MHz. This pin has an active pull down resistor of typically 400 kΩ and can be left floating for 2.8 MHz operation.
4 PG O Power good open drain output. This pin is high impedance if the output voltage is within regulation. This pin is pulled low if the output is below its nominal value. The pull up resistor can not be connected to any voltage higher than the input voltage of the device.
5 FB I Feedback pin of the device.
For the adjustable version, connect a resistor divider to set the output voltage.
For the fixed output voltage versions this pin may be connected to GND for improved thermal performance and has a pull down resistor of typically 400 kΩ, which is active when EN is low.
6 AGND Analog ground.
7 CP I/O Internal charge pump flying capacitor. Connect a 10 nF capacitor between CP and CN.
8 CN I/O Internal charge pump flying capacitor. Connect a 10 nF capacitor between CP and CN.
9 SS I Softstart control pin. A capacitor is connected to this pin and sets the softstart time. Leaving this pin floating sets the minimum start-up time.
10 AVIN I Bias supply input voltage pin.
11,12 PVIN I Power supply input voltage pin.
13 EN I Device enable. To enable the device this pin needs to be pulled high. Pulling this pin low disables the device. This pin has a pull down resistor of typically 400 kΩ, which is active when EN is low.
14,15 PGND Power ground connection.
16 VOS I Output voltage sense pin. This pin needs to be connected to the output voltage.
Exposed Thermal Pad – The exposed thermal pad is connected to AGND. It must be soldered for mechanical reliability.
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