The TPS2663x devices support the reverse input polarity protection feature. Connect an N-channel power FET (Q1) with the source to IN_SYS, drain to IN and GATE to B-GATE as shown in Figure 8-7. This action forms a back to back FET topology in power path that is required to protect the load from input reverse polarity faults. Connect an external signal FET (Q2) across BGATE, DRV and IN_SYS. Q2 acts as a pulldown gate switch for Q1. In the applications where reverse polarity protection and reverse current blocking is not required then connect IN_SYS and IN together. Leave BGATE and DRV open as shown in Figure 8-8.
Figure 8-9 illustrates the reverse input polarity protection functionality.

The TPS2663x devices support a maximum differential voltage across V_{(IN_SYS)} – V_(OUT) up to –85 V. This high voltage transients generally appear during the IEC61000-4-5 surge testing at the V_{(IN_SYS)}. This voltage stress appears across the external N-channel FET. The TPS2663x provides a gate drive (B_GATE) of 10.2 V (typical). The fast pulldown gate switch Q2 pulls down the GATE of the Q1 during reverse current and reverse polarity fault events. Q2 must be at least 15-V, VDS rated FET with a maximum VGS rating of 20 V, Ciss ≤ 50 pF and VGTH(min) ≤ 3 V.

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Figure 8-7 Configuration for Input Reverse Polarity Protection and Reverse Current Blocking

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Figure 8-8 Configuration for Applications Without Input Reverse Polarity Protection and Reverse Current Blocking Requirement

Figure 8-9 Input Reverse Polarity Response at –60-V Input