SLVSE94G September   2018  – June 2024

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Hot Plug-In and Inrush Current Control
        1. 8.3.1.1 Thermal Regulation Loop
      2. 8.3.2  PGOOD and PGTH
        1. 8.3.2.1 PGTH as VOUT Sensing Input
      3. 8.3.3  Undervoltage Lockout (UVLO)
      4. 8.3.4  Overvoltage Protection (OVP)
      5. 8.3.5  Input Reverse Polarity Protection (B_GATE, DRV)
      6. 8.3.6  Reverse Current Protection
      7. 8.3.7  Overload and Short-Circuit Protection
        1. 8.3.7.1 Overload Protection
          1. 8.3.7.1.1 Active Current Limiting at 1 × IOL (TPS26630 and TPS26632 Only)
          2. 8.3.7.1.2 Active Current Limiting With 2 × IOL Pulse Current Support (TPS26631, TPS26633, TPS26635, TPS26636, and TPS26637 Only)
        2. 8.3.7.2 Short-Circuit Protection
          1. 8.3.7.2.1 Start-Up With Short Circuit on Output
      8. 8.3.8  Output Power Limiting, PLIM (TPS26632, TPS26633, TPS26635, TPS26636, and TPS26637 Only)
      9. 8.3.9  Current Monitoring Output (IMON)
      10. 8.3.10 FAULT Response (FLT)
      11. 8.3.11 IN_SYS, IN, OUT, and GND Pins
      12. 8.3.12 Thermal Shutdown
      13. 8.3.13 Low Current Shutdown Control (SHDN)
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application: Power Path Protection in a PLC System
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Programming the Current-Limit Threshold—R(ILIM) Selection
        2. 9.2.2.2 Undervoltage Lockout and Overvoltage Set Point
        3. 9.2.2.3 Output Buffer Capacitor – COUT
        4. 9.2.2.4 PGTH Set Point
        5. 9.2.2.5 Setting Output Voltage Ramp Time—(tdVdT)
          1. 9.2.2.5.1 Support Component Selections— RPGOOD and C(IN)
        6. 9.2.2.6 Selecting Q1, Q2 and TVS Clamp for Surge Protection
      3. 9.2.3 Application Curves
    3. 9.3 System Examples
      1. 9.3.1 Simple 24-V Power Supply Path Protection
      2. 9.3.2 Priority Power MUX Operation
      3. 9.3.3 Input Protection for a Compact 24-V Auxiliary Power Supply for Servo Drives
    4. 9.4 Dos and Do Nots
    5. 9.5 Power Supply Recommendations
      1. 9.5.1 Transient Protection
    6. 9.6 Layout
      1. 9.6.1 Layout Guidelines
      2. 9.6.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

8.3.4 Overvoltage Protection (OVP)

The TPS2663x devices incorporate circuitry to protect the system during overvoltage conditions. The TPS26630 and TPS26631 feature an accurate ±2% adjustable overvoltage cutoff functionality. A voltage more than V(OVPR) on OVP pin turns off the internal FET and protects the downstream load. To program the OVP threshold externally, connect a resistor divider from IN_SYS supply to OVP terminal to GND as shown in the Simplified Schematic.

The TPS26630 and TPS26631 also feature a factory set 34.3-V input overvoltage cutoff V(IN_SYS_OVP) threshold with a 440-mV hysteresis. This feature can be enabled by connecting the OVP terminal directly to the GND terminal. The TPS26632, TPS26633 and TPS26636 feature an internally fixed 35-V maximum overvoltage clamp V(OVC) functionality. The TPS26632 and TPS26633 clamps the output voltage to V(OVC) when the input voltage exceeds 35 V. TPS26635 features a fixed 39-V maximum overvoltage clamp level. During the output voltage clamp operation, the power dissipation in the internal MOSFET is PD = (V(IN_SYS) – V(OVC)) × I(OUT). Excess power dissipation for a prolonged period can increase the device temperature. To avoid this increase, the internal FET is operated in overvoltage clamp for a maximum duration of tOVC(dly), 162 ms (typical). After this duration, the internal FET is turned OFF and the subsequent operation of the device depends on the MODE configuration (auto-retry or latch-off) setting as shown in Table 8-1.

Figure 7-1 shows the turn-ON behavior when OVP pin voltage falls below V(OVPF) threshold.

Figure 8-5 illustrates the overvoltage cutoff functionality and Figure 8-6 illustrates the overvoltage clamp functionality. FLT is asserted after a delay of 617 µs (typical) after entering in overvoltage clamp mode and remains asserted until the overvoltage fault is removed.

TPS2663 Overvoltage Cutoff Response at 33-V Level
TPS26630 and TPS26631
Figure 8-5 Overvoltage Cutoff Response at 33-V Level
TPS2663 Overvoltage Clamp Response With TPS26635
TPS26635 RLOAD = 30 Ω, FLT connected to VOUT
Figure 8-6 Overvoltage Clamp Response With TPS26635
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