For ±500-V, 2-Ω surge, typically a SMC sized TVS like SMCJ36CA clamps the voltage around ±55 V. During the negative surge strike, the input voltage V_{IN_SYS} spikes to –55 V. This spike results in a voltage stress of –(55 V + 24 V) = –79 V across the external blocking FET Q1. Choose at least a 80-V rated N-channel FET. B_GATE drive is in the range of 10 V to 14 V. Select a suitable FET with the target RDSON specified at this gate drive voltage. The fast pulldown gate switch Q2 pulls down the GATE of the Q1 during the reverse current event appearing during the surge test. Q2 must be at least 15-V VDS rated FET with a maximum VGS rating of 20-V , Ciss <= 50 pF and VGTH(min) ≤ 3 V. CSD19537Q3 and BSS138 are selected for Q1 and Q2 respectively. Figure 9-9 and Figure 9-10 illustrate the performance of the system during the surge testing.