Figure 3-1 through Figure 3-3 show the TPS54331EVM-232 board layout. The top-side layer of the EVM is laid out in a manner typical of a user application. The top and bottom layers are 2-oz. copper.

The top layer contains the main power traces for VIN, OUT, and VPHASE. Also on the top layer are connections for the remaining pins of the TPS54331 and a large area filled with ground. The bottom layer contains ground and a signal route for the BOOT capacitor. The top and bottom and internal ground traces are connected with multiple vias placed around the board including four vias directly under the TPS54331 device to provide a thermal path from the top-side ground traces to the bottom-side ground plane.

The input decoupling capacitors (C1, C2, and C3) and bootstrap capacitor (C4) are all located as close to the IC as possible. In addition, the voltage set-point resistor divider components are also kept close to the IC. The voltage divider network ties to the output voltage at the point of regulation, the copper VOUT trace past the output capacitor C3. For the TPS54331, an additional input bulk capacitor can be required, depending on the EVM connection to the input supply.

Figure 3-1 Top-Side Layout

Figure 3-2 Bottom-Side Layout (Looking From Top Side)

Figure 3-3 Top-Side Assembly