Figure 2-13 and Figure 2-14 show the start-up waveforms for the TPS54202EVM-716. In Figure 2-13, the output voltage ramps down as soon as the input voltage falls below the UVLO stop threshold as set by the R4 and R5 resistor divider network. In Figure 2-14, the output is inhibited by using a 3.3-V logic signal between EN and GND. The input voltage for these plots is 24 V and the load is 5 Ω.

Figure 2-13 TPS54202EVM-716 Shutdown Relative to V_IN

Figure 2-14 TPS54202EVM-716 Shutdown Relative to EN