Figure 2-11 and Figure 2-12 show the start-up waveforms for the TPS54202EVM-716. In Figure 2-11, the output voltage ramps up as soon as the input voltage reaches the UVLO threshold as set by the R4 and R5 resistor divider network. In Figure 2-12, the input voltage is initially applied and the output is inhibited by using a 3.3-V logic signal between EN and GND. When the EN voltage reaches the enable-threshold voltage, the start-up sequence begins and the output voltage ramps up to the externally set value of 5 V. The input voltage for these plots is 24 V and the load is 5 Ω.

Figure 2-11 TPS54202EVM-716 Startup Relative to V_IN

Figure 2-12 TPS54202EVM-716 Startup Relative to Enable