SLVUBI1 May 2021
Table 2-1 describes the default configuration of the TPS7H4002EVM-CVAL listing the external components that define the converter design.
| Parameter | Specifications | Description |
|---|---|---|
| Input power supply | 5 V | Bound by UVLO enable circuit (R13, R15) |
| Regulated output voltage |
2.5 V |
R7 (RTOP) = 10 kΩ, R5 (RBOTTOM) = 4.7 kΩ |
| LOUT |
2.2 µH |
Chosen to meet inductor ripple current of 40% (Kind = 0.4) |
| COUT | 330 µF | Chosen for (1) ESR = 6 mΩ to set output voltage
ripple; (2) value used during single event effects testing ensuring regulation maintained with single event upset to switching |
| Output current | 0 to 3 A | By design |
| Switching frequency | 500 kHz | Set by R10 (RT) = 95.3 kΩ |
| Soft start time constant | ≈ 3.2 ms | Set by C1 (Css) = 10 nF |
| UVLO enable rising | ≈ 4.432 V | Set by R13 = 10 kΩ and R15 = 3.4 kΩ |
| UVLO enable falling | ≈ 4.284 V | Set by R13 = 10 kΩ and R15 = 3.4 kΩ |
| Loop bandwidth | ≈ 30 kHz | Set by operational transconductance amplifier (OTA) compensation circuit: R14 (RCOMP) = 11.8 kΩ, C14 (CCOMP) = 22 nF, C6 (CHF) = 22 pF |
| Loop phase margin | ≈ 60° | |
| Gain margin | ≈ –25 dB |