SLVUBW7 May 2020
Table 1 describes the default configuration of the TPS7H4001QEVM-CVAL listing the external components that define the complete parallel converter design.
| PARAMETER | SPECIFICATIONS | DESCRIPTION |
|---|---|---|
| Input power supply | 5 V | Bound by UVLO enable circuit (R5, R6) |
| Regulated output voltage | 1 V | R19 (RTOP) = 10 kΩ, R26 (RBOTTOM) = 15.4 kΩ |
| LOUT per converter | 0.9 µH | Chosen to meet inductor ripple current of 10% (Kind = 0.1) |
| COUT per converter | 1980 µF | Chosen for (1) ESR = 1 mΩ to set output voltage ripple; (2) value used during single event effects testing ensuring regulation maintained with single event upset to switching |
| Output current per converter | 0 to 18 A | By design |
| Switching frequency | 500 kHz | Set by R9 (RT) = 174 kΩ |
| Soft start time constant | ≈2 ms | Set by C13 (Css) = 39 nF |
| UVLO enable rising | ≈4.249 V | Set by R5 = 10 kΩ and R6 = 3.4 kΩ |
| UVLO enable falling | ≈4.011 V | Set by R5 = 10 kΩ and R6 = 3.4 kΩ |
| Loop bandwidth | ≈25 kHz | Set by operational transconductance amplifier (OTA) compensation circuit: R7 (RCOMP) = 2 kΩ, C15 (CCOMP) = 33 nF, C14 (CHF) = 330 pF |
| Loop phase margin | ≈60° | |
| Gain margin | ≈–25 dB |