SLVUBZ2A September 2020 – December 2020 LM5127-Q1
Table 4-1 lists the EVM jumper descriptions.
| Jumper | Name | Description |
|---|---|---|
| J1 | VCH1A | When CH1 is configured as a boost controller this jumper is the connection for the input power for the boost controller. When CH1 is configured as a buck controller this is the output voltage for the buck controller |
| J2 | VCH1B | When CH1 is configured as a boost controller this jumper is the connection for the output power for the boost controller. When CH1 is configured as a buck controller this is the input voltage for the buck controller |
| J3 | SS1 | Populating this jumper will enable diode emulation mode (DEM) on CH1 |
| J4 | PGOOD1/PGOOD2/PGOOD3 | Probe points for PGOOD1, PGOOD2, PGOOD3. An external 5 V must be applied between TP10 and TP11 for these signals to be active |
| J5 | VCCX | Bias voltage connection to the VCCX pin from one of the output channels on the board. Connecting pin 1 and pin 2 biases the VCCX with VCH1A. This connection is typically made when CH1 is configured as a buck controller. Connecting pin 3 and pin 4 biases the VCCX with VOUT2. Connecting pin 5 and pin 6 biases the VCCX with VOUT3. |
| J6 | EN1 | Input to enable or disable CH1. Connecting pin 1 and pin 2 enables CH1 by connecting the EN1 pin to the BIAS pin. Connecting pin 2 to pin 3 disables CH1 by connecting EN1 to GND. |
| J7 | EN2 | Input to enable or disable CH2. Connecting pin 1 and pin 2 enables CH2 by connecting the EN2 pin to the BIAS pin. Connecting pin 2 to pin 3 disables CH2 by connecting EN2 to GND. |
| J8 | EN3 | Input to enable or disable CH3. Connecting pin 1 and pin 2 enables CH3 by connecting the EN3 pin to the BIAS pin. Connecting pin 2 to pin 3 disables CH3 by connecting EN3 to GND. |
| J9, J10, J11 | PGND | Power ground connections for oscilloscope measurements. |
| J12 | SYNC/DITHER/VCC_HOLD | Configures the SYNC/Dither/VCC_HOLD pin based on the application specifications. Connecting pin 1 and pin 2 will enable the VCC hold functionality. Connecting a function generator between pin 2 and pin 3 allows for external clock synchronization if C34 is removed and J14 is left open. J14 and J12 should not be populated at the same time. |
| J13 | RES | Configuration of the RES pin. Connecting pin 1 and pin 2 enables cycle by cycle peak current limiting with no hiccup mode. Connecting pin 2 and pin 3 latches the channel off until the appropriate enable pin is toggled. If the jumper is left of the hiccup mode time is determined by the value of capacitor connected to the RES pin (C34) |
| J14 | Dither | Leaving this jumper and J12 open enables frequency dithering functionality. When pin 1 and pin 2 are connected frequency dithering, external clock synchronization and VCC_HOLD are disabled. |
| J15 | CFG/MODE | This pin configures the LM5127 to the appropriate topology and switching mode for the application. For the standard configuration of this EVM the jump should be connected between pin 1 and pin 2 (SKIP) or between pin 5 and pin 6 (FPWM/DEM). See Table 4-3 for more detail on the device configuration. |
| J16 | VBUS | Input voltage rail of CH2 and CH3 buck controllers. VBUS can be tied to VCH1B by populating R33 with a 0Ω resistor. |
| J17 | VOUT2 | Output voltage connection of CH2 |
| J18 | SS2 | Populating this jumper will enable diode emulation mode (DEM) on CH2 |
| J19 | VOUT3 | Output voltage connection of CH3 |
| J20 | SS3 | Populating this jumper will enable diode emulation mode (DEM) on CH3 |
Table 4-2 lists the EVM test point descriptions.
| Test Point | Name | Description |
|---|---|---|
| TP1 | VCH1A | Positive voltage probe point for VCH1A |
| TP2 | VCH1B | Positive voltage probe point for VCH1B |
| TP3 | PGND | Ground probe point for VCH1B |
| TP4 | PGND | Ground probe point for VCH1A |
| TP5 | VCH1B (+) | CH1 loop response positive injection point |
| TP6 | VCH1B (-) | CH1 loop response negative injection point |
| TP7 | DIS/BMOUT | DIS/BMOUT pin probe point |
| TP8 | SS1 | SS1 pin probe point |
| TP9 | AGND | AGND probe point |
| TP10 | 5V_EXT (+) | Positive external 5V connection to pull PGOODx to 5V |
| TP11 | 5V_EXT (-) | Negative connection for external 5V PGOOD supply. |
| TP12 | VBUS | Positive voltage probe point for VBUS |
| TP13 | PGND | Ground probe point for VBUS |
| TP14 | VOUT2 | Positive voltage probe point for VOUT2 |
| TP15 | VOUT2(+) | CH2 loop response positive injection point |
| TP16 | VOUT2(-) | CH2 loop response negative injection point |
| TP17 | PGND | Ground probe point for VOUT2 |
| TP18 | SS2 | SS2 pin probe point |
| TP19 | VOUT3(+) | CH3 loop response positive injection point |
| TP20 | VOUT3 | Positive voltage probe point for VOUT3 |
| TP21 | VOUT3(-) | CH3 loop response negative injection point |
| TP22 | PGND | Ground probe point for VOUT3 |
| TP23 | SS3 | SS3 pin probe point |
Table 4-3 lists the LM5127-Q1 pin CFG/MODE connection details (J15).
| Configuration | Pin Connection | CH1 | CH2 | CH3 | Switching Mode |
|---|---|---|---|---|---|
| 1 (0Ω) 1 | 1 to 2 | Boost | Single Buck | Single Buck | Skip Mode |
| 2 (9.53kΩ) | 3 to 4 | Buck | |||
| 3 (19.1kΩ) 1 | 5 to 6 | Boost | FPWM/DEM | ||
| 4 (29.4kΩ) | 7 to 8 | Buck | |||
| 5 (41.2kΩ) | 9 to 10 | Boost | Dual Phase Buck | CH1: SkipCH2/CH3: FPWM/DEM | |
| 6 (54.9kΩ) | 11 to 12 | Buck | |||
| 7 (71.5kΩ) | 13 to 14 | Boost | FPWM/DEM | ||
| 8 (90.9kΩ) | 15 to 16 | Buck | |||