The C and D triggers, defined by the NSLEEPx bits or pins, trigger the TO_RETENTION sequence. This sequence disables all power rails and GPIOs that are not supplying the retention rails, as described in Figure 3-1. The sequence can be modified using the I2C_7 and I2C_6 bits found in register FSM_I2C_TRIGGERS. These bits need to be set by I²C before a trigger for the retention state occurs. If the I2C_7 bit is set high, the PMIC enters the DDR retention state. If I2C_6 bit is set high, the PMIC enters the GPIO retention state. TO_RETENTION sequence with GPIO and DDR retention is shown in Figure 6-7. If I2C_6 and I2C_7 are set low, the components associated with DDR and GPIO retention do not remain active, as shown in Figure 6-6.

The following PMIC PFSM instructions are executed automatically in the beginning of the power sequence to configure the PMIC:

// Clear NRSTOUT
REG_WRITE_MASK_IMM ADDR=0x81 DATA=0x00 MASK=0xFE
// Set SPMI_LP_EN and FORCE_EN_DRV_LOW
REG_WRITE_MASK_IMM ADDR=0x82 DATA=0x18 MASK=0xE7

At the end of the sequence, PMIC sets the LPM_EN and clears the CLKMON_EN and AMUXOUT_EN bits.