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SLVUCD4 November 2022 TPS6594-Q1

3.2 Control Mapping

Figure 3-2 shows the digital control signal mapping between processor, PMIC, and discrete power devices. Connections from the TPS65941515 PMIC to the processor provide error monitoring, processor reset, processor wake up, and system low-power modes. Specific GPIO pins have been assigned to key signals in order to ensure proper operation during low power modes when only a few GPIO pins remain operational.

The digital connections shown in Figure 3-2 allow system features including GPIO and DDR Retention modes, functional safety up to ASIL-D, and compliant dual voltage SD card operation.

Figure 3-2 TPS65941515-Q1 Digital Connections

PMIC IO can have distinct power domains for input and output functionality. The SDA function for I2C1 and I2C2 use the VINT voltage domain as an input and the VIO voltage domain as an output. Please refer to the device data sheet for a complete description. The PMIC voltage domains indicated are for the TPS65941515 NVM configuration.
PMIC_Wake1 is typically a CAN PHY INH output.
The EFUSE LDO is an optional feature and must be enabled by another signal in the system

Note: In addition to the I²C signals, three additional signals are open-drain outputs and require a pullup to a specific power rail. Please refer to Table 3-2 for a list of the signals and the specific power rail.

Table 3-2 Open-drain signals and Power Rail

PDN Signal	Pullup Power Rail
H_MCU_INTn_3V3	VDD_IO_3V3
H_SOC_PORz_1V8	VDA_LN_1V8
EN_DDR_RET_1V1	VDD_DDR_1V1_REG
H_WKUP_I2C0	VDD_IO_3V3
H_MCU_I2C0_SCL/SDA	VDD_IO_3V3

Please use Table 3-3 as a guide to understand GPIO assignments required for each PDN system feature. If the feature listed is not required, the digital connection can be removed; however, the GPIO pin is still configured per NVM defined default function shown. After the processor has booted up, the processor can reconfigure unused GPIOs to support new functions. Reconfiguring unused GPIOs is possible as long as that function is only needed after boot and default function does not cause any conflicts with normal operations (for example, two outputs driving same net). For details on how functional safety related connections help achieve functional safety system-level goals, see Section 4.

Table 3-3 Digital Connections by System Feature

Device	GPIO Mapping			System Features⁽¹⁾
Device	PMIC Pin	NVM Function	PDN Signals	Active SoC	Functional Safety	DDR Retention	GPIO Retention
TPS65941515-Q1	nPWRON/ ENABLE	Enable	SOC_PWR_ON	R
	INT	INT	H_MCU_INTn		R
	nRSTOUT	nRSTOUT	H_SOC_PORz_1V8	R
	SCL_I2C1	SCL_I2C1	H_WKUP_I2C0	R
	SDA_I2C1	SDA_I2C1	H_WKUP_I2C0	R
	GPIO_1	SCL_I2C2	H_MCU_I2C0_SCL		R
	GPIO_2	SDA_I2C2	H_MCU_I2C0_SDA		R
	GPIO_3	nERR_SoC	H_SOC_SAFETY_ERRn		O
	GPIO_4	LP_WKUP1⁽²⁾	PMIC_WAKE1			R	R
	GPIO_5	GPO	EN_GPIORET_VWK	R			R
	GPIO_6	GPO	EN_DDR_RET_1V1			R
	GPIO_7	nERR_MCU	H_MCU_SAFETY_ERRn		R
	GPIO_8	DISABLE_WDOG	PMICA_GPIO8	⁽³⁾	⁽³⁾
	GPIO_9	GPO	EN_GPIORET_VIO	R			R
	GPIO_10	CLK32OUT	H_WKUP_LFOSCO_XI	O
	GPIO_11	GPO	EN_SOC_VIO	R			R

(1) R is Required.

(2) LP_WKUP1 function is masked in the static settings. Instructions for unmasking the function are provided in RETENTION, Entering and Exiting Standby and Entering and Existing LP_STANDBY.

(3) If it is desired to disable the watchdog through hardware, GPIO_8 is required and must be set high by the time nRSTOUT goes high. After nRSTOUT is high, the watchdog state is latched and the pin can be configured for other functions through software. If GPIO_8 is not set high, then the processor must service the watch dog before the long window expires.