SLVUCF1A September   2022  – October 2022 TPSM63610

 

  1.   Abstract
  2.   Trademarks
  3. 1High-Density EVM Description
    1. 1.1 Typical Applications
  4. 2Test Setup and Procedure
    1. 2.1 EVM Connections
    2. 2.2 EVM Setup
    3. 2.3 Test Equipment
    4. 2.4 Recommended Test Setup
      1. 2.4.1 Input Connections
      2. 2.4.2 Output Connections
    5. 2.5 Test Procedure
      1. 2.5.1 Line, Load Regulation and Efficiency
  5. 3Test Data and Performance Curves
    1. 3.1 Efficiency and Load Regulation Performance
    2. 3.2 Waveforms
    3. 3.3 Bode Plot
    4. 3.4 EMI Performance
  6. 4EVM Documentation
    1. 4.1 Schematic
    2. 4.2 Bill of Materials
    3. 4.3 PCB Layout
    4. 4.4 Multi-Layer Stackup
  7. 5Device and Documentation Support
    1. 5.1 Device Support
      1. 5.1.1 Development Support
        1. 5.1.1.1 Custom Design With WEBENCH® Tools
    2. 5.2 Documentation Support
      1. 5.2.1 Related Documentation
  8. 6Revision History

3.3 Bode Plot

Figure 3-17 provides the bode plot at VIN = 24 V, VOUT = 5 V, FSW = 1 MHz, and IOUT = 8 A. Figure 3-18 shows a typical capacitance versus voltage curve for a 47-µF, 16-V, X6S output capacitor to highlight the effective capacitance value of a ceramic. See component details in Bill of Materials.

Figure 3-17 Bode Plot With Four 47-µF, 16-V Output Capacitors (110 µF Effective at 5 VDC, 25°C)
Figure 3-18 Output Capacitor Voltage Derating Curve
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