SLVUCH3 February   2023 TPS65219

 

  1.   ABSTRACT
  2.   Trademarks
  3. 1Introduction
  4. 2EEPROM Device Settings
    1. 2.1  Device ID
    2. 2.2  Enable Settings
    3. 2.3  Regulator Voltage Settings
    4. 2.4  Power Sequence Settings
      1. 2.4.1 Power Sequence Settings - Slot assignments
      2. 2.4.2 Power Sequence Settings - Slot Durations
      3. 2.4.3 TPS6521901 Sequence and Power Block Diagram
    5. 2.5  EN / PB / VSENSE Settings
    6. 2.6  Multi-Function Pin Settings
    7. 2.7  Over-Current Deglitch
    8. 2.8  Mask Settings
    9. 2.9  Discharge Check
    10. 2.10 Multi PMIC Config

2.4.1 Power Sequence Settings - Slot assignments

Table 2-6 Power-UP Sequence Settings - Slot Assignments
Register Name Field Name Value Description
BUCK1 BUCK1_SEQUENCE_SLOT BUCK1_SEQUENCE_ON_SLOT 0x5 slot 5
BUCK2 BUCK2_SEQUENCE_SLOT BUCK2_SEQUENCE_ON_SLOT 0x0 slot 0
BUCK3 BUCK3_SEQUENCE_SLOT BUCK3_SEQUENCE_ON_SLOT 0x4 slot 4
LDO1 LDO1_SEQUENCE_SLOT LDO1_SEQUENCE_ON_SLOT 0x2 slot 2
LDO2 LDO2_SEQUENCE_SLOT LDO2_SEQUENCE_ON_SLOT 0x6 slot 6
LDO3 LDO3_SEQUENCE_SLOT LDO3_SEQUENCE_ON_SLOT 0x2 slot 2
LDO4 LDO4_SEQUENCE_SLOT LDO4_SEQUENCE_ON_SLOT 0x2 slot 2
GPO1 GPO1_SEQUENCE_SLOT GPO1_SEQUENCE_ON_SLOT 0x2 slot 2
GPO2 GPO2_SEQUENCE_SLOT GPO2_SEQUENCE_ON_SLOT 0x0 slot 0
GPIO GPIO_SEQUENCE_SLOT GPIO_SEQUENCE_ON_SLOT 0x0 slot 0
nRSTOUT nRST_SEQUENCE_SLOT nRST_SEQUENCE_ON_SLOT 0x9 slot 9

Note: PMIC rails are turned ON during the power-up sequence if the corresponding EN bit on section "Enable Setting" is set to 0x01.

Table 2-7 Power-Down Sequence Settings - Slot Assignments
Register Name Field Name Value Description
BUCK1 BUCK1_SEQUENCE_SLOT BUCK1_SEQUENCE_OFF_SLOT 0x2 slot 2
BUCK2 BUCK2_SEQUENCE_SLOT BUCK2_SEQUENCE_OFF_SLOT 0x4 slot 4
BUCK3 BUCK3_SEQUENCE_SLOT BUCK3_SEQUENCE_OFF_SLOT 0x0 slot 0
LDO1 LDO1_SEQUENCE_SLOT LDO1_SEQUENCE_OFF_SLOT 0x2 slot 2
LDO2 LDO2_SEQUENCE_SLOT LDO2_SEQUENCE_OFF_SLOT 0x0 slot 0
LDO3 LDO3_SEQUENCE_SLOT LDO3_SEQUENCE_OFF_SLOT 0x2 slot 2
LDO4 LDO4_SEQUENCE_SLOT LDO4_SEQUENCE_OFF_SLOT 0x4 slot 4
GPO1 GPO1_SEQUENCE_SLOT GPO1_SEQUENCE_OFF_SLOT 0x2 slot 2
GPO2 GPO2_SEQUENCE_SLOT GPO2_SEQUENCE_OFF_SLOT 0x0 slot 0
GPIO GPIO_SEQUENCE_SLOT GPIO_SEQUENCE_OFF_SLOT 0x0 slot 0
nRSTOUT nRST_SEQUENCE_SLOT nRST_SEQUENCE_OFF_SLOT 0x0 slot 0
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