The board layout for the TPS56C231LEVM is shown in Figure 5-1 to Figure 5-5. The TPS56C231LEVM is with four layers. The top layer contains the main power traces for VIN, VOUT, SW, and GND. Also, on the top layer are connections for the pins of the TPS56C231L and a large area filled with ground. Most of the signal traces are also located on the top side. The input decoupling capacitors are located as close to the VIN pins and PGND pins of the IC as possible. The internal layer-1 is dedicated ground plane. The internal layer-2 contains an additional large ground copper area as well as an additional VIN and VOUT copper fill. The bottom layer is a ground plane along with 4 traces for VIN, VOUT, EN, and BOOT connection.