SLVUCM0 august   2023 TPS65219

 

  1.   1
  2.   ABSTRACT
  3.   Trademarks
  4. 1Introduction
  5. 2PDN and Sequence Diagrams
    1. 2.1 TPS6521908 Sequence and Power Block Diagram
  6. 3EEPROM Device Settings
    1. 3.1  Device ID
    2. 3.2  Enable Settings
    3. 3.3  Regulator Voltage Settings
    4. 3.4  Sequence Settings
      1. 3.4.1 Power-Up Sequence
      2. 3.4.2 Power-Down Sequence
    5. 3.5  EN / PB / VSENSE Settings
    6. 3.6  Multi-Function Pin Settings
    7. 3.7  Over-Current Deglitch
    8. 3.8  Mask Settings
    9. 3.9  Discharge Check
    10. 3.10 Multi PMIC Config

3.1 Device ID

This section lists all the register settings to identify the supported temperature and the NVM ID with the corresponding revision that represent a list of default register settings.

Table 3-1 Device ID
Register Name Field Name Value Description
TI_DEV_ID TI_DEVICE_ID 0x00 Device specific ID code to identify supported ambient and junction temperature.
NVM_ID TI_NVM_ID 0x08 Identification code for the NVM ID
FACTORY_CONFIG_2 NVM_REVISION 0x2 Identification code for the NVM revision
I2C_ADDRESS_REG I2C_ADDRESS 0x30 I2C address
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