SLVUCN8 april 2023 TPS65219-Q1
This section describes the PMIC rails that are enabled in Active and Standby state. Any rail that is disabled by default has the option to be enabled through I2C once the device is in Active state and I2C communication is available.
| PMIC Rail | Register Name | Field Name | Value | Description |
|---|---|---|---|---|
| BUCK1 | ENABLE_CTRL | BUCK1_EN | 0x1 | Enabled |
| BUCK2 | ENABLE_CTRL | BUCK2_EN | 0x1 | Enabled |
| BUCK3 | ENABLE_CTRL | BUCK3_EN | 0x1 | Enabled |
| LDO1 | ENABLE_CTRL | LDO1_EN | 0x1 | Enabled |
| LDO2 | ENABLE_CTRL | LDO2_EN | 0x1 | Enabled |
| LDO3 | ENABLE_CTRL | LDO3_EN | 0x1 | Enabled |
| LDO4 | ENABLE_CTRL | LDO4_EN | 0x1 | Enabled |
| GPO1 | GENERAL_CONFIG | GPO1_EN | 0x0 | GPO1 disabled. The output state is low. |
| GPO2 | GENERAL_CONFIG | GPO2_EN | 0x1 | GPO2 enabled. The output state is Hi-Z. |
| GPIO | GENERAL_CONFIG | GPIO_EN | 0x0 | GPIO disabled. The output state is low. |
| PMIC Rail | Register Name | Field Name | Value | Description |
|---|---|---|---|---|
| BUCK1 | STBY_1_CONFIG | BUCK1_STBY_EN | 0x1 | Enabled in STBY Mode |
| BUCK2 | STBY_1_CONFIG | BUCK2_STBY_EN | 0x1 | Enabled in STBY Mode |
| BUCK3 | STBY_1_CONFIG | BUCK3_STBY_EN | 0x1 | Enabled in STBY Mode |
| LDO1 | STBY_1_CONFIG | LDO1_STBY_EN | 0x1 | Enabled in STBY Mode |
| LDO2 | STBY_1_CONFIG | LDO2_STBY_EN | 0x1 | Enabled in STBY Mode |
| LDO3 | STBY_1_CONFIG | LDO3_STBY_EN | 0x1 | Enabled in STBY Mode |
| LDO4 | STBY_1_CONFIG | LDO4_STBY_EN | 0x1 | Enabled in STBY Mode |
| GPO1 | STBY_2_CONFIG | GPO1_STBY_EN | 0x0 | Disabled in STBY Mode |
| GPO2 | STBY_2_CONFIG | GPO2_STBY_EN | 0x1 | Enabled in STBY Mode |
| GPIO | STBY_2_CONFIG | GPIO_STBY_EN | 0x0 | Disabled in STBY Mode |