SLVUCR7 September   2024 TPS26750

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     National Conventions
    3.     Glossary
    4.     Related Documents
    5.     Support Resources
    6.     Trademarks
  3. 1Introduction
    1. 1.1 Introduction
      1. 1.1.1 Purpose and Scope
    2. 1.2 PD Controller Host Interface Description
      1. 1.2.1 Overview
      2. 1.2.2 Register and field notation
    3. 1.3 Unique Address Interface
      1. 1.3.1 Unique Address Interface Protocol
  4. 2PD Controller Policy Modes
    1. 2.1 Overview
    2. 2.2 Source Policy Mode
    3. 2.3 Sink Policy Mode
  5. 3Register Overview
  6. 4TPS26750 Registers
  7. 54CC Task Detailed Descriptions
    1. 5.1 Overview
    2. 5.2 CPU Control Tasks
      1. 5.2.1 'Gaid' - Return to normal operation
      2. 5.2.2 'GAID' - Cold reset request
    3. 5.3 PD Message Tasks
      1. 5.3.1  'SWSk' - PD PR_Swap to Sink
      2. 5.3.2  'SWSr' - PD PR_Swap to Source
      3. 5.3.3  'SWDF' - PD DR_Swap to DFP
      4. 5.3.4  'SWUF' - PD DR_Swap to UFP
      5. 5.3.5  'GSkC' - PD Get Sink Capabilities
      6. 5.3.6  'GSrC' - PD Get Source Capabilities
      7. 5.3.7  'ESkC' - PD EPR Get Sink Capabilities
      8. 5.3.8  'ESrC' - PD EPR Get Source Capabilities
      9. 5.3.9  'GPPI' - PD Get Port Partner Information
      10. 5.3.10 'SSrC' - PD Send Source Capabilities
      11. 5.3.11 'MBRd' - Message Buffer Read
    4. 5.4 Patch Bundle Update Tasks
      1. 5.4.1 'PBMs' - Start Patch Burst Mode Download Sequence
      2. 5.4.2 'PBMc' - Patch Burst Mode Download Complete
      3. 5.4.3 'PBMe' - End Patch Burst Mode Download Sequence
      4. 5.4.4 'GO2P' - Go to Patch Mode
      5. 5.4.5 'FLrd' - Flash Memory Read
      6. 5.4.6 'FLad' - Flash Memory Write Start Address
      7. 5.4.7 'FLwd' - Flash Memory Write
      8. 5.4.8 'FLvy' - Flash Memory Verify
    5. 5.5 System Tasks
      1. 5.5.1 'DBfg' - Clear Dead Battery Flag
      2. 5.5.2 'I2Cr' - I2C read transaction
      3. 5.5.3 'I2Cw' - I2C write transaction
      4. 5.5.4 'GPsh' - set GPIO high
      5. 5.5.5 'GPsl' - set GPIO low
  8. 6User Reference
    1. 6.1 PD Controller Application Customization
    2. 6.2 Loading a Patch Bundle
    3. 6.3 AUTO_NEGOTIATE_SINK Register
      1. 6.3.1 AUTO_NEGOTIATE_SINK usage example #1
      2. 6.3.2 AUTO_NEGOTIATE_SINK usage example #2
      3. 6.3.3 AUTO_NEGOTIATE_SINK usage example #3
      4. 6.3.4 AUTO_NEGOTIATE_SINK usage example #4
    4. 6.4 IO_CONFIG Register
      1. 6.4.1 GPIO Events
  9. 7Revision History

'PBMc' - Patch Burst Mode Download Complete

Table 5-16 'PBMc' - Patch Burst Download Complete
DescriptionThe 'PBMc' Task ends the patch loading sequence. Send this Task after all patch data has been transferred. This Task will initiate the CRC check on the binary patch data that has been transferred, and if the CRC is successful, the patch_init function contained within the patch will be executed.
INPUT DATAXNone
OUTPUT DATAXBitNameDescription
319:288acCalculatedCRCThe CRC calculated in FW for the configuration data.
287:256acTransferredCRCThe CRC transferred along with the configuration data
255:240Reservedreads as 0
239:224acIndicatedDataSizeThe indicated DataSize in the transferred configuration data.
223:216acHeaderVersionThe indicated header version in the transferred configuration data.
215:208acFailCodeAn error code indicating why the app config data failed to apply, if it failed to apply
0x00AC_FAIL_NONE: No failure
0x01AC_FAIL_WRONG_HEADER_VERSION: The header version is expected to be 1 and was not
0x02AC_FAIL_TOO_MUCH_DATA: The DataSize field indicates that you are trying to load more configuration data that there is allocated SRAM for
0x03AC_FAIL_CRC_CHECK_FAIL: The CRC comparison failed
207:200acStateThe current internal state of the AppConfig state machine
0x00AC_NODATA: No configuration data found yet, because we haven't started looking
0x01AC_LOADING_DEFAULT: Attempting to load configuration data from a factory default
0x02AC_LOADING_SRAM: Attempting to load configuration data from SRAM
0x03AC_LOADING_FLASH: Attempting to load configuration data from Flash
0x04AC_LOADING_I2C: Attempting to load configuration data from I2C
0x05AC_LOADING_DONE: Done loading configuration data, we found valid data
0x06AC_ERROR: A generic error state
0x07AC_DONE_SUCCESS: Completely done with the app customization process and the records were applied successfully.
0x08AC_DONE_FAIL: Completely done with the app customization process and the records were not applied
199:192configBundleGood1 if the top-level state machine found a valid configuration bundle, otherwise 0.
191:160rpRomVersionExpectedThe romVersionExpected in the transferred bundle's patch header
159:144rpBundleTotalSizeThe bundleTotalSize in the transferred bundle's patch header
143:128rpBundleFlagsThe bundleFlags in the transferred bundle's patch header
127:96rpPatchBodyCrcThe patchBodyCrc in the transferred bundle's patch header
95:64rpPatchHeaderCrcThe patchHeaderCrc in the transferred bundle's patch header
OUTPUT DATAXBitNameDescription
55:48rpBundleSignatureThe bundleSignature in the transferred bundle's patch header
47:40rpStateThe current internal state of the RomPatch state machine.
0x00RP_NOPATCH: No patch has been loaded
0x01RP_LOADING: In the process of loading patch data
0x02RP_LOADINGDONE: All patch data has been received
0x03RP_RUNNING: A patch has been loaded and is running. Could also indicate that a NULL patch is active.
0x04RP_EARLYLOAD_SKIPPED: Indicates that the early boot process does not need to wait for a patch over I2C
0x05RP_UARTBOOTED: Checking for a patch in RAM
0x06RP_ERROR: A generic error state
39:32patchBundleGood0x01 if the top-level state machine found a good ROM patch, otherwise 0x00.
31:24AppConfigPatchCompleteStatus0x00
0x40Warning
0x80Failure
23:16DevicePatchCompleteStatus

A return code indicating whether the RomPatch state machine executed successfully.

This value is always valid, and reflective of the internal state of the RomPatch mechanism, but must only be considered if the bundle transferred did in fact include patch data.
0x00Success
0x20Not ready
0x40Not a patch
0x41Patch header checksum mismatch
0x42Patch not compatible with this version of ROM
0x43Patch code checksum mismatch
0x44Null patch received
0x45Error patch received
15:8cpReturnAlways returns success, there is no way for it to fail.
Byte 1: Return Code
7:4rpReturnIndicatorThe most significant nibble of the rpReturn value.
0x0Success
0x2Informational
0x4Warning
0x8Error
3:0acReturnIndicatorThe most significant nibble of the acReturn value.
0x0Success
0x2Informational
0x4Warning
0x8Error
Task CompletionThe 'PBMc' Task completes as output has a valid DevicePatchCompleteStatus and AppConfigPatchCompleteStatus. This Task is rejected if the DATAX input does not contain the total patch size. If MODE register (0x03) is equal to 'APP ', then this Task will be rejected.
Side EffectsBefore this Task completes it will change the I2C target address from the patch address back to the normal value. Upon successful completion of this Task the PD controller will change the MODE register (0x03) to 'APP ' and move to the application mode.
Additional InformationWhen the CMDx register goes to 0 check the Output DATAX register for status. If the MODE register is 'APP ' indicating that the PD controller is in the APP mode, then it will reject the 'PBMc' Task.