SLVUCR8A September 2023 – March 2024 TPS25751
| Description | The 'I2Cw' task can be used to cause the PD controller to write a particular I2C transaction using I2Cc_SDA and I2Cc_SCL. | ||
|---|---|---|---|
| INPUT DATAX | Bit | Name | Description |
| Bytes 5-14: Payload for the I2C transaction | |||
| Byte 4: Register Offset for the I2C transaction | |||
| 7:0 | Register offset | ||
| Bytes 2-3: Length | |||
| 15:8 | Reserved | ||
| 7:0 | Number of bytes in the transaction payload. | ||
| Byte 1: Target Address | |||
| 7 | Reserved | ||
| 6:0 | Target to use for the transaction. | ||
| OUTPUT DATAX | Byte 1: Standard Task Return Code | ||
| Task Completion | The PD controller maintains a queue of transactions to send on the I2Cc port. If the PD controller has been configured to send transactions upon certain events, it is possible there is a transaction in the queue when the 'I2Cw' task is received. In that case the task will complete successfully after the transaction is inserted into the queue. If the PD controller fails to insert the task into the queue for any reason, the task is rejected. Therefore, when this task is completed successfully it does not guarantee that the I2C transaction is complete. If possible, the host must use the 'I2Cr' 4CC task to confirm the write was successful. | ||
| Side Effects | When successful, this task will cause the PD controller to issue a command on the I2Cc port. This can result in INT_EVENTx.I2CControllerNACKed being asserted. | ||
| Additional Information | If the DATAX register is written with more than 14 bytes, all bytes beyond byte 14 are ignored. The PD controller has a limit on the maximum length of the I2C write transaction. The 'I2Cw' command cannot be sent within 5s from sending a previous 'I2Cw' command. This allows the PD controller to complete all I2C transactions. | ||