米6体育平台手机版

SLVUCZ4 September 2024 TPS65219

1
Abstract
Trademarks
1Introduction
2PDN and Sequence Diagrams
1. 2.1 TPS6521909 Sequence and Power Block Diagram
3EEPROM Device Settings
4Revision History

2.1 TPS6521909 Sequence and Power Block Diagram

Figure 2-1 TPS6521909 Example Power Block Diagram

Note: LDO2 is only used to supply the 0.85V fixed domains (i.e VDDR_CORE) when VDD_CORE operates at 0.75V. VDD_CORE and VDDR_CORE are expected to be powered by the same source (Buck1) when VDD_CORE is operating at 0.85V.

Figure 2-2 TPS6521909 digital connections to AM62A

Note:

PMIC digital signals that require external pull-up resistors: nRSTOUT, nINT, GPO1, VSEL(to set the LDO1 start up voltage as 3.3V), MODE/STBY (to define the Bucks switching operation), I2C pins (SCL/SDA).

Figure 2-3 TPS6521909 Power-Up Sequence

Figure 2-4 TPS6521909 Power-Down Sequence