SLWS230E September   2011  – December 2015

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 4WI Timing: Write Operation
    7. 6.7 Readback 4WI Timing
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Lock Detect
      2. 7.3.2 LO Divider
      3. 7.3.3 Selecting the VCO and VCO Frequency Control
      4. 7.3.4 External VCO
    4. 7.4 Device Functional Modes
      1. 7.4.1 VCO_TEST_MODE
      2. 7.4.2 Readback Mode
      3. 7.4.3 Integer and Fractional Mode Selection
      4. 7.4.4 PLL Architecture
        1. 7.4.4.1 Selecting PLL Divider Values
        2. 7.4.4.2 Setup Example for Integer Mode
        3. 7.4.4.3 Setup Example for Fractional Mode
      5. 7.4.5 Fractional Mode Setup
    5. 7.5 Register Maps
      1. 7.5.1 PLL 4WI Registers
        1. 7.5.1.1 Register 1
          1. 7.5.1.1.1 CAL_CLK_SEL[3..0]
          2. 7.5.1.1.2 ICP[4..0]
        2. 7.5.1.2 Register 2
          1. 7.5.1.2.1 PLL_DIV <1.0>
          2. 7.5.1.2.2 VCOSEL_MODE
        3. 7.5.1.3 Register 3
        4. 7.5.1.4 Register 4
        5. 7.5.1.5 Register 5
        6. 7.5.1.6 Register 6
      2. 7.5.2 Readback from the Internal Register Banks
        1. 7.5.2.1 Register 0 Write
          1. 7.5.2.1.1 Register 0 Read
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedures
        1. 8.2.2.1 Power Supply
        2. 8.2.2.2 Loop Filter
        3. 8.2.2.3 Reference Clock
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Trademarks
    2. 11.2 Electrostatic Discharge Caution
    3. 11.3 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

4 Revision History

Changes from D Revision (January 2013) to E Revision

  • Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section Go
  • Changed Bit27 through Bit30 of Table 7 From: B[25.21] To: B[30..27] Go

Changes from C Revision (December 2011) to D Revision

  • Changed the Description of Bit25 and Bit26 in Register 6Go
  • Changed the Description of Bit27 and Bit28 in Register 6Go
  • Changed the Bit Name of Bit31 From: DIV_MUX_BIAS_OVRT To: DIV_MUX_BIAS_OVRD in Register 6Go
  • Changed VCC_OSC From: +3.3V/5.0V To: +3.3V, and VCC_TK From: +3.3V To: +3.3V/5.0V in Go

Changes from B Revision (November 2011) to C Revision

  • Changed Reference Oscillator Parameters, Reference input impedance parameter rows in Electrical Characteristics tableGo
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