SLWU086C November 2013 – January 2016 ADS42JB46 , ADS42JB49 , ADS42JB69 , DAC38J84
The TSW14J56 EVM has one connector to allow for the direct plug in of TI JESD204B serial interface ADC and DAC EVMs. The specifications for this connector are mostly derived from the ANSI/VITA 57.1 FPGA Mezzanine Card (FMC) Standard. This standard describes the compliance requirements for a low-overhead protocol bridge between the IO of a mezzanine card and an FPGA processing device on a carrier card. This specification is being used by FPGA vendors on their development platforms.
The FMC connector, J4, provides the interface between the TSW14J56EVM and the ADC or DAC EVM under test. This 400-pin Samtec high-speed, high-density connector (part number SEAF-40-05.0-S-10-2-A-K) is suitable for high-speed differential pairs up to 21 Gbps.
In addition to the JESD204B standard signals, several CMOS single-ended signals and LVDS differential signals are connected between the FMC and FPGA. In the future, these signals may allow the HSDC Pro GUI to control the SPI serial programming of ADC and DAC EVMs that support this feature. The connector pinout description is shown in Table 4.
| FMC Signal Name | FMC Pin | Standard JESD204 Application Mapping | Description |
|---|---|---|---|
| RX0_P/N | C6 and C7 | Lane 0± (M → C) | JESD Serial data transmitted from mezzanine and received by carrier |
| RX1_P/N | A2 and A3 | Lane 1± (M → C) | JESD Serial data transmitted from mezzanine and received by carrier |
| RX2_P/N | A6 and A7 | Lane 2± (M → C) | JESD Serial data transmitted from mezzanine and received by carrier |
| RX3_P/N | A10 and A11 | Lane 3± (M → C) | JESD Serial data transmitted from mezzanine and received by carrier |
| RX4_P/N | A14 and A15 | Lane 4± (M → C) | JESD Serial data transmitted from mezzanine and received by carrier |
| RX5_P/N | A18 and A19 | Lane 5± (M → C) | JESD Serial data transmitted from mezzanine and received by carrier |
| RX6_P/N | B16 and B17 | Lane 6± (M → C) | JESD Serial data transmitted from mezzanine and received by carrier |
| RX7_P/N | B12 and B13 | Lane 7± (M → C) | JESD Serial data transmitted from mezzanine and received by carrier |
| RX8_P/N | B8 and B9 | Lane 8± (M → C) | JESD Serial data transmitted from mezzanine and received by carrier |
| RX9_P/N | B4 and B5 | Lane 9± (M → C) | JESD Serial data transmitted from mezzanine and received by carrier |
| TX0_P/N | C2 and C3 | Lane 0± (C → M) | JESD Serial data transmitted from carrier and received by mezzanine |
| TX1_P/N | A22 and A23 | Lane 1± (C → M) | JESD Serial data transmitted from carrier and received by mezzanine |
| TX2_P/N | A26 and A27 | Lane 2± (C → M) | JESD Serial data transmitted from carrier and received by mezzanine |
| TX3_P/N | A30 and A31 | Lane 3± (C → M) | JESD Serial data transmitted from carrier and received by mezzanine |
| TX4_P/N | A34 and A35 | Lane 4± (C → M) | JESD Serial data transmitted from carrier and received by mezzanine |
| TX5_P/N | A38 and A39 | Lane 5± (C → M) | JESD Serial data transmitted from carrier and received by mezzanine |
| TX6_P/N | B36 and B37 | Lane 6± (C → M) | JESD Serial data transmitted from carrier and received by mezzanine |
| TX7_P/N | B32 and B33 | Lane 7± (C → M) | JESD Serial data transmitted from carrier and received by mezzanine |
| TX8_P/N | B28 and B29 | Lane 8± (C → M) | JESD Serial data transmitted from carrier and received by mezzanine |
| TX9_P/N | B24 and B25 | Lane 9± (C → M) | JESD Serial data transmitted from carrier and received by mezzanine |
| GBTCLK0_M2C_P/N | D4 and D5 | DEVCLKA± (M → C) | Primary carrier-bound reference clock required for FPGA giga-bit transceivers. Equivalent to device clock. |
| GBTCLK1_M2C_P/N | B20 and B21 | Alt. DEVCLKA± (M → C) | Alternate Primary Carrier-bound reference clock required for FPGA giga-bit transceivers. For use when DEVCLKA (M → C) is not available |
| Device Clock, SYSREF, and SYNC | |||
| CLK_LA0_P/N | G6 and G7 | DEVCLKB± (M → C) | Secondary carrier-bound device clock. Used for special FPGA functions such as sampling SYSREF |
| LA01_P/N_CC | D8 and D9 | DEVCLK± (C → M) | Mezzanine-bound device clock. Used for low noise conversion clock |
| SYSREF_P/N | G9 and G10 | SYSREF± (M → C) | Carrier-bound SYSREF signal |
| LA05_P/N | D11 and D12 | SYSREF± (C → M) | Mezzanine-bound SYSREF signal |
| RX_SYNC_P/N | G12 and G13 | SYNC± (C → M) | ADC mezzanine-bound SYNC signal for use in class 0/1/2 JESD204 systems |
| TX_SYNC_P/N | F10 and F11 | DAC SYNC± (M → C) | Carrier-bound SYNC signal for use in class 0/1/2 JESD204 systems |
| TX_ALT_SYNC_P/N | F19 and F20 | Alt. DAC SYNC± (M → C) | Alternate carrier-bound SYNC signal for use in class 0/1/2 JESD204B systems |
| RX_ALT_SYNC_P/N | H31 and H32 | Alt. SYNC± (C → M) | Alternate ADC mezzanine-bound SYNC signal. For use when SYNC (C → M) is not available |
| SYNC | K22 | DAC SYNC (M → C) | Carrier-bound CMOS-level SYNC signal for use in class 0/1/2 JESD204 systems |
| Special Purpose I/O | |||
| PG_M2C_A | F1 | Power good from mezzanine to carrier | |
| CLK0_M2C_P/N | H4 and H5 | GPIO clock | |
| CLK1_M2C_P/N | G2 and G3 | GPIO clock | |
All other signals not mentioned in Table 4 can be used as general purpose I/O, either as single-ended signals or differential pairs. The ANSI/VITA 57.1 standard assigns voltages to certain pins. These are labeled as 12V, 3P3V, and VADJ nets on the connector page of the schematic. On the TSW14J56, these pins are connected to test points to allow the user to provide voltages at these pin locations.