SLWU086C November 2013 – January 2016 ADS42JB46 , ADS42JB49 , ADS42JB69 , DAC38J84
The TSW14J56 has 9 SMA connectors. The connectors are defined below:
| J6 | GBTCLK0N | Spare Transceiver reference clock negative input |
| J5 | GBTCLK0P | Spare Transceiver reference clock positive input |
| J13 | TRIG_IN | Adjustable level CMOS trigger input. Default level is 1.8 V |
| J7 | TRIG_OUT_A | Adjustable level CMOS trigger output. Default level is 1.8 V |
| J8 | TRIG_OUT_B | Adjustable level CMOS trigger output. Default level is 1.8 V |
| J12 | TRIG_OUT_C | Adjustable level CMOS trigger output. Default level is 1.8 V |
| J3 | REF_OSC_IN | AC coupled spare input connected to FPGA CLK input |
| J14 | EXT_SYSREFP | Spare SYSREF positive input to FPGA |
| J15 | EXT_SYSREFN | Spare SYSREF negative input to FPGA |