1 Introduction

The LMK5C33216 device is a high-performance network clock generator, synchronizer, and jitter attenuator with advanced reference clock selection and hitless switching capabilities designed to meet the stringent requirements of communications infrastructure applications.

This document contains the summary of the test setups and measured results highlighting compliance to ITU-T G.8262 (Timing characteristics of a synchronous Ethernet equipment slave clock) standard. The device-under-test (LMK5C33216) was configured using Texas Instruments' TICS Pro Silicon EVM Programming Tool. Unless specified otherwise, the LMK5C33216 Digital PLL loop bandwidth for EEC-Option 1 was set to 10 Hz and for EEC-Option 2 to 0.1 Hz.

All measurement results included in this document are for DPLL1. The measurement results for DPLL1 are an accurate representation of compliance characteristics for all three DPLLs. All three DPLLs passed standard compliance test requirements.

Throughout this document, the acronym MTIE stands for maximum time interval error and the acronym TDEV stands for time deviation.

Testing was performed using the Calnex Rb/GPS frequency reference and Calnex Paragon-T hardware. Other test hardware was used as required for the measurements.

Notable features of this high-performance device includes:

• Hitless Switching with minimal phase transients (< 100 ps)
• Ultra High-Performance VCO allows use of a low-cost holdover reference without sacrificing performance
• High-Performance DPLL Channel with Programmable loop bandwidth for jitter and wander filtering suitable for EEC Option 1 and EEC Option 2
• Reference Priority Selection, Gapped Clock and Runt Pulse Detectors, Automatic/Manual Switchover, Holdover, and Tuning Word History