A PLL that is locked to an input clock must be able to tolerate the jitter defined in figure 9 in the G.8262 specification and figure 10 in the G.8262 specification. The definition of tolerance is that the device will not trigger any alarms while locked to such an input clock and that it will be able to pull-in to such an input clock. For Option 1, LMK5C33216 DPLL loop bandwidth was set to 10 Hz. For Option 2, the DPLL loop bandwidth was set to 0.1 Hz. For this test, the modulation frequency and frequency deviation was applied on the E4437B.

In compliance with the jitter tolerance specification requirement, the reference clock to LMK5C33216 (generated using E4437B) was modulated. The LMK5C33216 met the jitter tolerance requirements per the standard. The LMK5C33216 did not trigger any alarms, stayed locked to the reference and there was no observed degradation to the integrated RMS (12 kHz to 20 MHz) phase jitter of the output clock (156.25 MHz). The integrated RMS phase jitter was < 250 fs (max) for the duration for this test.